DDFSTOP 094 W A Display data fetch stop (horiz. position)
DDFSTRT 092 W A Display data fetch start (horiz. position)
These registers control the horizontal timing of the
beginning and end of the bit plane DMA display data
fetch. The vertical bit plane DMA timing is identical
to the display windows described above.
The bit plane modules are dependent on the bit plane
horizontal size and on this data-fetch window size.
Register bit assignment
BIT 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00
---------------------------------------------------
USE X X X X X X X X H8 H7 H6 H5 H4 H3 X X
(X bits should always be driven with 0 to maintain
upward compatibility)
The Tables below show the start and stop timing for
different register contents.
DDFSTRT (left edge of display data fetch)
PURPOSE H8,H7,H6,H5,H4
---------------------------------
Extra wide (max) * 0 0 1 0 1
Wide 0 0 1 1 0
Normal 0 0 1 1 1
Narrow 0 1 0 0 0
DDFSTOP (right edge of display data fetch)
PURPOSE H8,H7,H6,H5,H4
---------------------------------
Narrow 1 1 0 0 1
Normal 1 1 0 1 0
Wide (max) 1 1 0 1 1
DIWSTOP 090 W A Display window stop (lower right
vertical-horizontal position)
DIWSTRT 08E W A Display window start (upper left
vertical-horizontal position)
These registers control display window size and
position by locating the upper left and lower right
corners.
BIT 15,14,13,12,11,10,09,08,07,06,05,04,03,02,01,00
---------------------------------------------------
USE V7 V6 V5 V4 V3 V2 V1 V0 H7 H6 H5 H4 H3 H2 H1 H0
DIWSTRT is vertically restricted to the upper 2/3
of the display (V8=0) and horizontally restricted to
the left 3/4 of the display (H8=0).
DIWSTOP is vertically restricted to the lower 1/2
of the display (V8=/V7) and horizontally restricted
to the right 1/4 of the display (H8=1).
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