JOYTEST 036 W D Write to all four joystick-mouse counters at once.
Mouse counter write test data:
BIT# 15,14,13,12,11,10,09,08 07,06,05,04,03,02,01,00
----------------------------------------------------
0DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
1DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx
POT0DAT 012 R P Pot counter data left pair (vert,horiz)
POT1DAT 014 R P Pot counter data right pair (vert,horiz)
These addresses each read a pair of 8-bit pot counters.
(Four counters total.) The bit assignment for both
addresses is shown below. The counters are stopped by
signals from two controller connectors (left-right)
with two pins each.
BIT# 15,14,13,12,11,10,09,08 07,06,05,04,03,02,01,00
-----------------------------------------------------
RIGHT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
LEFT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X7 X6 X5 X4 X3 X2 X1 X0
CONNECTORS PAULA
----------------------------------------
Loc. Dir. Sym Pin Pin# Pin Name
----------------------------------------
RIGHT Y RY 9 36 (POT1Y)
RIGHT X RX 5 35 (POT1X)
LEFT Y LY 9 33 (POT0Y)
LEFT X LX 5 32 (POT0X)
POTGO 034 W P Pot port data write and start.
POTGOR 016 R P Pot port data read (formerly called POTINP).
This register controls a 4-bit bi-directional I/O port
that shares the same four pins as the four pot counters
above.
BIT# FUNCT DESCRIPTION
---------------------------------------
15 OUTRY Output enable for Paula pin 36
14 DATRY I/O data Paula pin 36
13 OUTRX Output enable for Paula pin 35
12 DATRX I/O data Paula pin 35
11 OUTLY Output enable for Paula pin 33
10 DATLY I/O data Paula pin 33
09 OUTLX Output enable for Paula pin 32
08 DATLX I/O data Paula pin 32
07-01 0 Reserved for chip ID code (presently 0)
00 START Start pots (dump capacitors, start counters)
REFPTR 028 W A Refresh pointer
This register is used as a dynamic RAM refresh address generator. It is
writeable for test purposes only, and should never be written by
the microprocessor.
- 276 Appendix A -