Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 - Page 104

8 ELECTRICAL CHARACTERISTICS
A-88 EPSON S1C33L03 PRODUCT PART
SRAM read cycle (basic cycle: 1 cycle)
BCLK
A[23:0]
#CEx
#RD
D[15:0]
#WAIT
t C3
t AD
t CE1 t CE2
t RDD2 t RDD1
t RDAC1
t RDS
t WTS t WTH
t RDH
t CEAC1
t ACC1
t RDW
t AD
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∗1
*1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and
A[23:0] signals.
SRAM read cycle (when a wait cycle is inserted)
BCLK
A[23:0]
#CEx
#RD
D[15:0]
#WAIT
C1 Cw (wait cycle) Cn (last cycle)
t AD
t CE1 t CE2
t RDD2 t RDD1 (C1 only)
t RDAC1
t RDS
t WTS t WTH t WTS t WTH
t RDH
t CEAC1
t ACC1
t RDW
t AD
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∗1
t WTS t WTH
*1 tRDH is measured with respect to the first signal change (negation) from among the #RD, #CEx and
A[23:0] signals.