Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 User Manual

VII LCD CONTROLLER BLOCK: LCD CONTROLLER
S1C33L03 FUNCTION PART EPSON B-VII-2-19
A-1
B-VII
LCDC
Frame Rates
The frame rate is calculated from the LCD panel’s resolution, non-display period, and pixel clock frequency, as
shown below.
f
PCLK
Frame rate = ————————————————
(HDP + HNDP) × (VDP + VNDP)
f
PCLK: PCLK frequency (Hz)
This is the input clock frequency for the LCD controller derived by dividing the BCU clock. The BCU-clock
division ratio can be set to 1/1, 1/2, 1/3, or 1/4 using the LCLKSEL[2:0] (D[2:0])/FIFO control register
(0x39FFF4). The LCD controller supports a PCLK clock of up to 25 MHz.
HDP: Horizontal display period
This is the LCD panel’s horizontal resolution (in pixels). From the set value of LDHSIZE[5:0]
(D[5:0])/horizontal panel size register (0x39FFE4), the horizontal display period is calculated as follows:
Horizontal display period = (LDHSIZE[5:0] + 1) × 16 (Ts) where Ts = PCLK clock cycle
HNDP: Horizontal non-display period
This is a non-display period before the LCD panel starts displaying the next line after it has finished
displaying all pixels in one line. Set a value in 8 pixel units in the HNDP[4:0] (D[4:0])/horizontal non-display
period register (0x39FFE7).
Horizontal non-display period = (HNDP[4:0] + 4) × 8 (Ts)
The value HDP described above plus HNDP comprises the number of PCLK clock cycles per one-line period
(FPLINE pulse period).
VDP: Vertical display period
This is the LCD panel’s vertical resolution (number of display lines). From the set value of the
LDVSIZE[9:0] (D[9:0])/vertical panel size register (0x39FFE6, 0x39FFE5), the vertical display period is
calculated as follows:
Vertical display period = LDVSIZE[9:0] + 1 (lines)
VNDP: Vertical non-display period
This is a non-display period before the LCD panel starts displaying the next frame after it has finished
displaying all display lines in one frame. Set this period based on the number of lines in the VNDP[5:0]
(D[5:0])/vertical non-display period register (0x39FFEA).
Vertical non-display period = VNDP[5:0] (lines)
From the above parameters, we obtain the number of PCLK clock cycles required for the display of one frame, as
determined by (HDP + HNDP) × (VDP + VNDP). The frame rate is calculated by dividing the PCLK clock
frequency by this value.

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Specifications

General

Brand	Epson
Model	CMOS 32-Bit Single Chip Microcomputer S1C33L03
Category	Computer Hardware
Language	English