Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 User Manual

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-121
A-1
A-ap
A.3 ROM and Burst ROM
Burst ROM and mask ROM interface setup examples
Operating Normal read cycle Burst read cycle Output disable
frequency Wait cycle Read cycle Wait cycle Read cycle delay cycle
20MHz 2 3 1 2 1.5
25MHz 3 4 1 2 1.5
33MHz 4 5 2 3 1.5
Burst ROM and mask ROM interface timing
Burst ROM and mask ROM interface 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
Access time tACC –100515041603150
#CE output delay time tCE –100515041603150
#OE output delay time tOE –504.51353.51402.5125
Burst access time tBAC –503902802100
Output disable delay time tDF 0401.545 1.5 60 1.5 75
ROM: 100ns, CPU: 33MHz, normal read
t ACC
t CE
t OE
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0]
RD data
;;;;;
;;;;;
;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;
;;;;
;;;;
t DF
ROM: 100ns, CPU: 33MHz, burst read
Normal read cycle Burst read cycle
t BAC t BAC t BAC
BCLK
A[23:0]
#CE9, 10
#RD
D[15:0]
RD data
;;;
;;;
;;;;;;;;
;;;;;;;;
;;;
;;;
RD data
;;;;;
;;;;;
RD data
;;;;;
;;;;;
RD data
;;;;;
;;;;;
t DF

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Specifications

General

Brand	Epson
Model	CMOS 32-Bit Single Chip Microcomputer S1C33L03
Category	Computer Hardware
Language	English