Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 - SRAM (55 Ns

APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
S1C33L03 PRODUCT PART EPSON A-123
A-1
A-ap
A.4 SRAM (55ns)
SRAM interface setup examples – 55ns
Operating Read cycle Output disable
frequency Wait cycle Read cycle
Write cycle
delay cycle
20MHz 1 2 2 1.5
25MHz 2 3 3 1.5
33MHz 2 3 3 1.5
SRAM interface timing – 55ns
SRAM interface 33MHz 25MHz 20MHz
Parameter Symbol Min. Max. Cycle Time Cycle Time Cycle Time
<Read cycle>
Read cycle time tRC 55 – 3 90 3 1202100
Address access time tACC –5539031202100
#CE access time tACS –5539031202100
#OE access time tOE –302.5752.5 100 1.5 75
Output disable delay time tOHZ 0301.545 1.5 60 1.5 75
<Write cycle>
Write cycle time tWC 55 – 3 90 3 1202100
Address enable time tAW 50 – 2.5 75 2.5 100 1.5 75
Write pulse width tWP 45 – 2 60 2 80 1 50
Input data setup time tDW 30 – 2 60 2 80 1 50
Input data hold time tDH 0–0.5150.520 0.5 25
SRAM: 55ns, CPU: 33/25MHz, read cycle
tRC
tACC
tACS
tOE
BCLK
A[23:0]
#CEx
#RD
D[15:0]
RD data
;;;;;
;;;;;
;;;;;;;;;
;;;;;;;;;
;;;;
;;;;
tOHZ
SRAM: 55ns, CPU: 33/25MHz, write cycle
tWC
tAW
tWP
tDW
BCLK
A[23:0]
#CEx
#WR
D[15:0]
WR data
;;;;;
;;;;;
;;;
;;;
tDH