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Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 - Page 120

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03
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8 ELECTRICAL CHARACTERISTICS
A-104 EPSON S1C33L03 PRODUCT PART
Frame Pulse
Line Pulse
Sync Timing
t
2
t
1
t
6b
t
6a
t
8
t
9
t
7a
t
7b
t
14
t
11
t
10
t
12
t
13
t
12
t
13
t
4
t
3
Line Pulse
Shift Pulse 2
Shift Pulse
FPDAT[7:0]
Data Timing
1 2
8-bit Single Color Panel AC Timing (Format 1)
Symbol Parameter Min. Typ. Max. Unit
t1 Frame Pulse setup to Line Pulse falling edge note 2 (note 1)
t2 Frame Pulse hold from Line Pulse falling edge 9 Ts
t3 Line Pulse period note 3
t4 Line Pulse width 9 Ts
t6a Shift Pulse falling edge to Line Pulse rising edge note 4
t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5
t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6
t7b Shift Pulse falling edge to Line Pulse falling edge note 7
t8 Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge t14+2 Ts
t9 Shift Pulse 2, Shift Pulse period 4 Ts
t10 Shift Pulse 2, Shift Pulse width low 2 Ts
t11 Shift Pulse 2, Shift Pulse width high 2 Ts
t12 FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge 1 Ts
t13 FPDAT[7:0] hold from Shift Pulse 2, Shift Pulse falling edge 1 Ts
t14 Line Pulse falling edge to Shift Pulse 2 rising edge 23 Ts
note) 1.Ts = pixel clock period
2.t
1min = t3min - 9 (Ts)
3.t
3min = (LDHSIZE[5:0] + 1) × 16 + (HNDP[4:0] + 4) × 8 + 1 (Ts)
4.t
6amin = HNDP[4:0] × 8 + t13 - t10 + 1 (Ts)
5.t
6bmin = HNDP[4:0] × 8 + t13 + 1 (Ts)
6.t
7amin = HNDP[4:0] × 8 + 11 (Ts)
7.t
7bmin = HNDP[4:0] × 8 + 11 - t10 (Ts)

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