II CORE BLOCK: ITC (Interrupt Controller)
B-II-5-24 EPSON S1C33L03 FUNCTION PART
SIO3ES1:SIO Ch.3 receive error/TM16 Ch.3 compare A interrupt factor switching
(D5) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": SIO Ch.3 receive error
Write "0": TM16 Ch.3 compare A
Read: Valid
Set to "1" to use the SIO Ch.3 receive error interrupt.
Set to "0" to use the TM16 Ch.3 compare A interrupt.
At power-on, this bit is set to "0".
T8CH4S1:8-bit timer 4 underflow/TM16 Ch.2 compare B interrupt factor switching
(D6) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": 8-bit timer 4 underflow
Write "0": TM16 Ch.2 compare B
Read: Valid
Set to "1" to use the 8-bit timer 4 underflow interrupt.
Set to "0" to use the TM16 Ch.2 compare B interrupt.
At power-on, this bit is set to "0".
T8CH5S1:8-bit timer 5 underflow/TM16 Ch.2 compare A interrupt factor switching
(D7) / Interrupt factor TM16 function switching register (0x402CB)
Switches the interrupt factor.
Write "1": 8-bit timer 5 underflow
Write "0": TM16 Ch.2 compare A
Read: Valid
Set to "1" to use the 8-bit timer 5 underflow interrupt.
Set to "0" to use the TM16 Ch.2 compare A interrupt.
At power-on, this bit is set to "0".
TBRP7–TBRP0: TTBR register write protection ([D[7:0]) / TTBR write-protect register (0x4812D)
Remove write protection for the TTBR register.
Write 0x59: Write protection is removed
Write not the above: No operation (write protected)
Read: Valid
Before writing to the TTBR register, set TBRP to "0x59" to remove the write protection. Then when data is written
to the most significant byte (0x48137) of the TTBR, the register once again becomes write-protected.
After an initial reset, TBRP is set to "0x0" (write protected).
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