Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 User Manual

III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33L03 FUNCTION PART EPSON B-III-8-37
A-1
B-III
SIF
RDBF0: Ch.0 receive data buffer full (D0) / Serial I/F Ch.0 status register (0x401E2)
RDBF1: Ch.1 receive data buffer full (D0) / Serial I/F Ch.1 status register (0x401E7)
RDBF2: Ch.2 receive data buffer full (D0) / Serial I/F Ch.2 status register (0x401F2)
RDBF3: Ch.3 receive data buffer full (D0) / Serial I/F Ch.3 status register (0x401F7)
Indicates the status of the receive data register (buffer).
Read "1": Buffer full
Read "0": Buffer empty
Write: Invalid
RDBFx is set to "1" when the data received in the shift register is transferred to the receive data register (receive
operation completed), indicating that the received data can be read out. This bit is reset to "0" when the data is read
out.
At initial reset, RDBFx is set to "0" (buffer empty).
TXEN0: Ch.0 transmit enable (D7) / Serial I/F Ch.0 control register (0x401E3)
TXEN1: Ch.1 transmit enable (D7) / Serial I/F Ch.1 control register (0x401E8)
TXEN2: Ch.2 transmit enable (D7) / Serial I/F Ch.2 control register (0x401F3)
TXEN3: Ch.3 transmit enable (D7) / Serial I/F Ch.3 control register (0x401F8)
Enables each channel for transmit operations.
Write "1": Transmit enabled
Write "0": Transmit disabled
Read: Valid
When TXENx for a channel is set to "1", the channel is enabled for transmit operations. When TXENx is set to "0",
the channel is disabled for transmit operations.
Always make sure the TXENx = "0" before setting the transfer mode and other conditions.
At initial reset, TXENx is set to "0" (transmit disabled).
RXEN0: Ch.0 receive enable (D6) / Serial I/F Ch.0 control register (0x401E3)
RXEN1: Ch.1 receive enable (D6) / Serial I/F Ch.1 control register (0x401E8)
RXEN2: Ch.2 receive enable (D6) / Serial I/F Ch.2 control register (0x401F3)
RXEN3: Ch.3 receive enable (D6) / Serial I/F Ch.3 control register (0x401F8)
Enables each channel for receive operations.
Write "1": Receive enabled
Write "0": Receive disabled
Read: Valid
When RXENx for a channel is set to "1", the channel is enabled for receive operations. When RXENx is set to "0",
the channel is disabled for receive operations.
Always make sure the RXENx = "0" before setting the transfer mode and other conditions.
At initial reset, RXENx is set to "0" (receive disabled).

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Specifications

General

Brand	Epson
Model	CMOS 32-Bit Single Chip Microcomputer S1C33L03
Category	Computer Hardware
Language	English