Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03

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IV ANALOG BLOCK: A/D CONVERTER

B-IV-2-8 EPSON S1C33L03 FUNCTION PART

Trap vector

The A/D converter's interrupt trap-vector default address is set to 0x0C00100.

The base address of the trap table can be changed using the TTBR register (0x48134 to 0x48137).

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Default Chapter5
- Table of Contents5
- S1C33L03 Product Part15
Outline17
- Features17
- Block Diagram19
- Pin Description20
  - Pin Layout Diagram (Plastic Package20
  - Pin Functions21
Power Supply28
- Power Supply Pins28
- Operating Voltage28
  - DD Ss28
  - Dde28
- Power Supply for Analog Circuits (AV DDE29
Internal Memory30
- ROM and Boot Address30
- Ram31
Peripheral Circuits32
- List of Peripheral Circuits32
- I/O Memory Map33
Power-Down Control81
Basic External Wiring Diagram84
Precautions on Mounting85
Electrical Characteristics87
- Absolute Maximum Rating87
- Recommended Operating Conditions88
- DC Characteristics89
- Current Consumption91
- A/D Converter Characteristics92
- AC Characteristics94
- Oscillation Characteristics123
- PLL Characteristics124
Package125
- Plastic Package125
Pad Layout126
- Pad Layout Diagram126
- Pad Coordinate127
Appendix A <Reference> External Device Interface Timings129
- DRAM (70Ns130
- DRAM (60Ns133
- ROM and Burst ROM137
- SRAM (55Ns139
- SRAM (70Ns141
- 8255A143
Appendix B Pin Characteristics144
Ioutline149
Introduction151
Block Diagram153
List of Pins155
- List of External I/O Pins155
- Core Block163
Introduction165
Cpu and Operating Mode167
- Cpu167
- Standby Mode168
Initial Reset173
- Pins for Initial Reset173
- Cold Start and Hot Start173
- Power-On Reset174
- Reset Pulse174
- Boot Address175
- Notes Related to Initial Reset175
BCU (Bus Control Unit)177
- Pin Assignment for External System Interface177
- Bus Clock193
  - Bus Speed Mode194
  - Bus Clock Output194
- Bus Cycles in External System Interface195
- DRAM Direct Interface200
- Releasing External Bus208
- Power-Down Control by External Device209
- I/O Memory of BCU210
ITC (Interrupt Controller)225
- Outline of Interrupt Functions225
- Trap Table228
- Control of Maskable Interrupts229
- IDMA Invocation233
- HSDMA Invocation235
- I/O Memory of Interrupt Controller236
- Programming Notes249
CLG (Clock Generator)251
- Configuration of Clock Generator251
- I/O Pins of Clock Generator252
- High-Speed (OSC3) Oscillation Circuit252
- Pll253
- Controlling Oscillation253
- Setting and Switching over the CPU Operating Clock254
- Power-Control Register Protection Flag255
- Operation in Standby Mode255
- I/O Memory of Clock Generator256
- Programming Notes259
DBG (Debug Unit)261
- Debug Circuit261
- I/O Pins of Debug Circuit261
- Peripheral Block263
Introduction265
Prescaler267
- Configuration of Prescaler267
- Source Clock267
- Selecting Division Ratio and Output Control for Prescaler268
- Source Clock Output to 8-Bit Programmable Timer268
- I/O Memory of Prescaler269
- Programming Notes274
8-Bit Programmable Timers275
- Configuration of 8-Bit Programmable Timer275
- Output Pins of 8-Bit Programmable Timers275
- Uses of 8-Bit Programmable Timers276
- Control and Operation of 8-Bit Programmable Timer278
- Control of Clock Output281
- 8-Bit Programmable Timer Interrupts and DMA282
- I/O Memory of 8-Bit Programmable Timers284
- Programming Notes291
16-Bit Programmable Timers293
- Configuration of 16-Bit Programmable Timer293
- I/O Pins of 16-Bit Programmable Timers294
- Uses of 16-Bit Programmable Timers295
- Control and Operation of 16-Bit Programmable Timer296
- Controlling Clock Output296
- Controlling Clock Output299
- 16-Bit Programmable Timer Interrupts and DMA301
- I/O Memory of 16-Bit Programmable Timers304
- Programming Notes317
Watchdog Timer319
- Configuration of Watchdog Timer319
- Control of Watchdog Timer319
- Operation in Standby Modes320
- I/O Memory of Watchdog Timer321
- Programming Notes321
Low-Speed (Osc1) Oscillation Circuit323
- Configuration of Low-Speed (OSC1) Oscillation Circuit323
- I/O Pins of Low-Speed (OSC1) Oscillation Circuit323
- Oscillator Types324
- Controlling Oscillation325
- Switching over the CPU Operating Clock325
- Power-Control Register Protection Flag326
- Operation in Standby Mode326
- OSC1 Clock Output to External Devices326
- I/O Memory of Low-Speed (OSC1) Oscillation Circuit327
- Programming Notes330
Clock Timer331
- Configuration of Clock Timer331
- Control and Operation of the Clock Timer332
- Interrupt Function334
- Examples of Use of Clock Timer336
- I/O Memory of Clock Timer337
- Programming Notes342
Serial Interface343
- Configuration of Serial Interfaces343
- Clock-Synchronized Interface346
- Asynchronous Interface354
- Irda Interface363
- Serial Interface Interrupts and DMA366
- I/O Memory of Serial Interface370
- Programming Notes388
Input/Output Ports389
- Input Ports (K Ports)389
- I/O Ports (P Ports)392
- Input Interrupt400
- Programming Notes413
Analog Block415
Introduction417
A/D Converter419
- Features and Structure of A/D Converter419
- I/O Pins of A/D Converter420
- Setting A/D Converter421
- Control and Operation of A/D Conversion423
- A/D Converter Interrupt and DMA425
- I/O Memory of A/D Converter427
- Programming Notes433
Dma Block435
Introduction437
HSDMA (High-Speed DMA)439
- Functional Outline of HSDMA439
- I/O Pins of HSDMA440
- Programming Control Information441
  - Setting the Registers in Dual-Address Mode441
  - Setting the Registers in Single-Address Mode444
- Enabling/Disabling DMA Transfer445
- Trigger Factor446
- Operation of HSDMA447
- Interrupt Function of HSDMA453
- I/O Memory of HSDMA455
- Programming Notes474
IDMA (Intelligent DMA)475
- Functional Outline of IDMA475
- Programming Control Information475
- IDMA Invocation479
- Operation of IDMA482
- Linking486
- Interrupt Function of Intelligent DMA487
- I/O Memory of Intelligent DMA488
- Programming Notes491
Sdram Controller Block493
Introduction495
Sdram Interface497
- Outline of SDRAM Interface497
- SDRAM Controller Block Diagram497
- I/O Pins and Connection498
  - I/O Pins498
  - Connection Examples498
- SDRAM Controller Configuration501
- SDRAM Operation508
- I/O Memory of SDRAM Interface517
- Programming Notes528
- Examples of SDRAM Controller Initialization Program529
Lcd Controller Block531
Introduction533
Lcd Controller535
- Overview535
  - Features535
  - Block Diagram537
- I/O Pins of the LCD Controller538
- System Settings539
- Setting the LCD Panel542
- Display Control555
- I/O Memory of LCD Controller565
- Programming Notes576
- Precautions on Using ICD33576
- Examples of LCD Controller Setting Program577
Appendix I/O Map579

Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 - Page 426

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