DAZZLER
TM
system manual Part I : installation & operation 8.7
• gentrig ”read trigger” a short pulse which triggers the RF cycle (ie ”gate” signal) if
the conditions allow it (power ok, protection period elapsed, ...). This pulse is useful to
debug lost triggers. The width of this pulse is the sampling period, ie. in the range 5-50
ns.
• fsmpdiv4 ”data sampling clock, divided by 4” can be used to synchronize external equip-
ment or to verify that the sampling clock is as expected (PLL locked in low jitter systems).
Older generators output the sampling clock. Slower signals fsmpcnt(4-5) are available on
S3-S4 for debugging.
• s1seqsync and s2seqsync ”sequence sync selection” reserved for synchronization in
sequence mode.
• auxcopy ”aux input copy” logical copy of the aux signal: used to verify operation of
aux.
• trigina ”trigger blocking” All external triggers received during trigina are inhibited.
Note that each trigger occuring within trigina restart the monostable for a period and
thus lengthen the signal. This is wanted to filter out rebounds, but will fail to recognize
any trigger if the frequency is above 1/trigina.
It is possible to adjust this
blocking time between 0.5µs and
10µs by using a jumper equipped
with a capacitor. Removing the
jumper is necessary to operate at
100kHz.
C2 nF t µs
10.00 8.2
2.20 5.0
1.50 4.1
1.00 3.1
0.68 2.4
1 0.47 1.8
• chop is a signal which can be used to perform an operation every N triggers. N can be
adjusted from 2 to 254 (default to 10 at power up). Use to be described in an ”separate”
note.
blue trace = trigina, red trace = gate, green trace = /(CHOP)
Figure 8.7: Generation of a logic high every CHOP cycles
V3.00 - 8
th
April 2019 (ContentsTable) (FiguresTable) 89/94
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