GPP Series User Manual
184
Event Registers
The operation, measurement and questionable status register
groups all have event registers. The event registers are read only
registers that reflect the status of the unit. Individual bits in the
event registers are latched (set) when a corresponding event occurs
and will remain latched even if the corresponding event changes, as
long as the event bit is still set. The register query (*ESR) or the
command (*CLS) will automatically clear any set bits in the event
registers. The reset command (*RST) will not clear the bits in the
event register. Queries for the event registers will return a binary-
weighted decimal value that represents the state of all the bits in an
event register.
Enable Registers
The enable registers define which bits in the corresponding event
register can be latched (set). The enable register can be read and
written to. Any queries for the enable register will not clear the
value in the register. The *CLS command will not clear the enable
register, but will clear the events in the event register. To allow the
individual bits in the event registers to be set, the corresponding
bits in the enable registers must be set, where each bit is
represented by a binary number.
Status Byte Register
The status byte register reports the status of the other status
registers. The message available bit (bit 4), will indicate when there
is a message in the output buffer. Clearing an event register will
clear the corresponding bit in the status byte condition register.
Reading all the data in the output buffer will clear the message
available bit. To set the enable register mask for the status byte
register and to generate an SRQ (service request) you must use the
*SRE command to write the appropriate decimal value to the
register.
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