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Subject to change without notice
Short Description of HM1508-2 Boards
Preliminary note:
This short description refers to the HM1508 block diagram. It
contains the most important functions, but not all.
1. TE Board
1.1 Probe identifi cation
The contact area around the BNC sockets (CH1 to CH4) is for
probe identifi cation contact recognition. The information from
the probe’s internal identifi cation resistor is input in the proces-
sor system and automatically changes parameters regarding
the probe’s divider ratio.
1.2 CALibrator Signal
The calibrator signal originates from the MC board, controls
the driver and is available at the PROBE ADJ socket.
2. YP Board
2.1 CH1 and CH2
The measuring signal at the input is connected through a swit-
chable high impedance attenuator, galvanically (DC coupled) or
via an input capacitor (AC coupled) to the input FET (impedance
converter). The following measuring amplifi er stages are DC
coupled.
The next stage is the Pre Amplifi er, where for 1 mV/cm and
2 mV/cm ranges, an additional amplifi cation by 5 is made.
The following low impedance attenuator allows the selection of all
Y defl ection coeffi cients from 1 mV/cm to 20 V/cm, in connection
with the high impedance attenuator and the Pre Amplifi er.
The fi xed Y defl ection coeffi cient can also be set to uncali-
brated intermediate values in the VAR Gain stage. Additio-
nally the signal is converted from an asymmetric signal into
2 symmetrical signals with a phase difference of 180°. The
following stages up to the Delay Line Driver are designed as
two identical amplifi ers.
The Symmetry and Trigger Pick Off stage is used to correct
asymmetries and thereafter the selection of the measurement
signal to be used for internal triggering.
If activated, the Inverting Switch reverses the 2 (180° different)
measuring signals to be amplifi ed in the following stages. The
result is a 180° turned (inverted) signal display.
In the Intermediate Amplifi er the DC current of both identical
amplifi ers is controlled in such a way, that if the current in one
amplifi er is reduced it increases in the other amplifi er by the
same amount. This causes a trace position shift in (Y position).
Thereafter the measuring signals of CH1 and CH2 are input in
the Channel Switch & Digital Pick Off stage. Before entering
the channel switch, the CH1 and CH2 measuring signals are
picked off and feed the channel 1 and 2 buffer amplifi ers on
AB board. The channel switch is active in analogue mode and
selects which signal is output and feeds the Delay Line Driver.
The channel switch is controlled by the Channel Switch, Driver
& CT Switch stage.
The Delay Line stage converts the signal to the wave resistance
stage of the delay line.
2.2 CH3 and CH4 (only digital)
The measuring signal at the input is connected to an FET (im-
pedance converter) galvanically (DC coupling) or via an input
capacitor (AC coupling).
In the following Comparator stages the state of the digital logic
input signals are compared with logic threshold voltages. The
comparison result of each comparator is connected to the
Control Unit FPGA on AB board.
2.3 Trigger Section
The CH1 and CH2 measuring signals originating from the
measuring amplifi er Trigger Pick Off are amplifi ed in the In-
termediate Trigger Amplifi er CH1 and CH2.
These signals later used for internal triggering are input in
the Trigger Channel Switch stage, which is active in analogue
and digital mode. The signal to be used for internal triggering
is selected by the switch.
This signal enters the Trigger Amplifi er stage for additional
amplifi cation.
The output signal is connected with the LF Filter, TV Sync. Se-
parator & Slope Selection and Trigger Coupling & Line Input
stage. The selected stage serves as the source for the TB A
(time base A) Trigger Comparator and the Trigger PP (peak to
peak) Circuit.
The Trigger Amplifi er output signal is also the DC coupled
source of the TB B Trigger Comparator (time base B) which
can be used in analog mode only.
The Trigger PP Circuit generates a signal height dependent
voltage that can be used for trigger level setting at the time
base A trigger comparator.
Both time base A and B reference voltages are generated by
the 10 bit D/A Converter on MB board.
The time base A and B trigger comparator output signals are
connected with the Time Base Control PLD on MB board for
analog time base triggering. Additionally the time base A trigger
comparator output signal is also connected with the Control
Unit FPGA on AB board for digital time base triggering.
2.4 Y Control
This stage encodes all control functions for attenuator, variable,
position, inverting and other Y amplifi er related functions.
2.5 Channel Switch, Driver and CT Switch
This stage encodes all control functions regarding the channel
switches, switches in the driver section and the component
tester (CT) switch over.
2.6 CT Y Coupling Switch
Switches the analogue measuring signal off in the Delay Line
Driver stage and inputs the vertical component of the compo-
nent tester (CT) signal.
3. Delay Line
3.1 The delay line introduces a delay of the analogue measu-
ring signal, so that switching and other delays in the trigger
Short Description of HM1508-2 Boards
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