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Hitachi 670 Series Application Guide

Hitachi 670 Series
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Section 6 Appendix
6.1 Sample specification of communication requirements
GUID-5F3AF242-270C-4FA2-8DA3-7A3532609D7B v1
This chapter provides a sample specification of communication requirements for line differential
protection IEDs in telecommunication networks. The requirements are based on echo timing.
Bit error rate (BER) according to ITU-T G.821, G.826 and G.828
< 10
-6
according to the standard for data and voice transfer
Bit error rate (BER) with high availability of the line differential protection
IED
< 10
-8
to 10
-9
during normal operation
< 10
-6
during disturbed operation
During disturbed operation, the trip security function in the line differential protection IED
can cope with high bit error rates up to 10
-5
or even up to 10
-4
. Trip security can be
configured to be independent from COMFAIL of the line differential protection
communication supervision, or it can be blocked when COMFAIL is issued after receive
error > 100 ms (default).
Synchronization in SDH systems with G.703 E1 or IEEE C37.94
G.703 E1 (2 Mbit/s) is set according to ITU-T G.803, G.810-13.
One master clock for the actual network
Actual port synchronized from the SDH system clock at 2048 kbit
Synchronization: bit synchronized, synchronized mapping
Maximum clock deviation: < ±50 ppm nominal, < ±100 ppm operational
Jitter and wander according to ITU-T G.823 and G.825
Buffer memory: < 250 μs, < 100 μs asymmetric difference
G.704 frame format: structured, unstructured, and so on
No CRC check
Synchronization in PDH systems connected to SDH systems
Independent synchronization, asynchronous mapping
Actual SDH port set to allow transmission of the master clock from the PDH network (SDH
network in transparent mode)
Maximum clock deviation: < ±50 ppm nominal, < ±100 ppm operational
Jitter and wander according to ITU-T G.823 and G.825
Buffer memory: <1 00 μs
Format: transparent
Maximum channel delay
Loop time: < 40 ms continuous (2 x 20 ms)
Line differential protection IED with echo synchronization (no GPS clock)
Both channels to have the same route with maximum asymmetry of 0.2–0.5 ms depending on
the set sensitivity of the line differential protection function
Fixed asymmetry can be compensated for by setting the AsymDelay on the local HMI or via PST
Line differential protection IED with GPS synchronization (GPS clock)
Independent of asymmetry
1MRK505382-UEN Rev. K Section 6
Appendix
Communication set-up, 670/650 series 93
Application Guide
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Hitachi 670 Series Specifications

General IconGeneral
BrandHitachi
Model670 Series
CategoryControl Unit
LanguageEnglish

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