Holtek BS66F340 - Page 174

Rev. 1.60 174 August 20, 2019 Rev. 1.60 175 August 20, 2019
BS66F340/BS66F350/BS66F360/BS66F370
Touch A/D Flash MCU with LED Driver
BS66F340/BS66F350/BS66F360/BS66F370
Touch A/D Flash MCU with LED Driver
Bit 3 RIDLE: Receiver status
0: data reception is in progress (data being received)
1: no data reception is in progress (receiver is idle)
The RIDLE ag is the receiver status ag. When this read only ag is "0", it indicates
that the receiver is between the initial detection of the start bit and the completion of
the stop bit. When the ag is "1", it indicates that the receiver is idle. Between the
completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1"
indicating that the UART receiver is idle and the RX pin stays in logic high condition.
Bit 2 RXIF: Receive RXR data register status
0: RXR data register is empty
1: RXR data register has available data
The RXIF ag is the receive data register status ag. When this read only ag is "0",
it indicates that the RXR read data register is empty. When the ag is "1", it indicates
that the RXR read data register contains new data. When the contents of the shift
register are transferred to the RXR register, an interrupt is generated if RIE=1 in the
UCR2 register. If one or more errors are detected in the received word, the appropriate
receive-related ags NF, FERR, and/or PERR are set within the same clock cycle. The
RXIF ag is cleared when the USR register is read with RXIF set, followed by a read
from the RXR register, and if the RXR register has no data available.
Bit 1 TIDLE: Transmission status
0: data transmission is in progress (data being transmitted)
1: no data transmission is in progress (transmitter is idle)
The TIDLE flag is known as the transmission complete flag. When this read only
ag is "0", it indicates that a transmission is in progress. This ag will be set to "1"
when the TXIF ag is "1" and when there is no transmit data or break character being
transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state
in logic high condition. The TIDLE ag is cleared by reading the USR register with
TIDLE set and then writing to the TXR register. The ag is not generated when a data
character or a break is queued and ready to be sent.
Bit 0 TXIF: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR data register is empty)
The TXIF ag is the transmit data register empty ag. When this read only ag is "0",
it indicates that the character is not transferred to the transmitter shift register. When
the ag is "1", it indicates that the transmitter shift register has received a character
from the TXR data register. The TXIF flag is cleared by reading the UART status
register (USR) with TXIF set and then writing to the TXR data register. Note that
when the TXEN bit is set, the TXIF ag bit will also be set since the transmit data
register is not yet full.