8-251.
MATE (CIIL) Block Circuit Description
8-252.
CLOCK
AND
LOGIC DRIVER. The MATE Block uses the reset circuit
in
the HP-IB Block (U292
and associated components) and the Clock and Logic Driver integrated circuits, U714E/F, U715C, and
U707BlCF to synchronize the microprocessor and microcomputers. The reset circuit holds the reset line for
microprocessor
U702
(pin
6)
LOW for at least 100 ms after the
+
5V supply reaches
+
4.8V. This 100 ms delay
allows U702 clock to stabiie.
8-253. ADDRESS LATCH. The U702 microprocessor has 16 address lines. Eight lines are dedicated to the ad-
dress bus and eight are shared with the data bus. The eight least significant bits of the address bus are multi-
plexed with the eight bit bidirectional data bus to one port of
U702. The Address Latch (U703), controlled by
U702 Address Strobe (AS) signal (pin
39),
is used to demultiplex the address.
8-254. DATA BUFFER. The &bit
bidirectional transceiver U704 is used for data transfers. The direction of
the transfer is determined by U702
R/W signal (pin
38),
and the outputs of U704 are enabled by the EDLY(L)
output of U715C (pin 8). The use of EDLY(L), a delayed and inverted system clock, assures the outputs of
U704 are three-stated during the address portion of the address cycle.
8-255.
READIWRITE DECODE. EPROM U709 has two enable lines, 15 address lines, and eight three-state
data lines. When an instruction is executed by
U702, the Reamrite Decode logic determines
if
EPROM U709
is being addressed. If so, the addressed data is placed on the data bus and is read on the falling edge of the sys-
tem clock. The
Reamrite Decode logic consists of, U712A, U714A, U707A, U715A, U714C, U712B, U715B,
U714D, U712D, U714B, U712C, and U713.
8-256.
U708
is
an 8K byte CMOS static
RAM.
It has two chip select lines, two enable lines, and 13 address
Lines. The Reamrite Decode logic determines if the RAM is being addressed and whether a read or write
cycle is being executed. During a read from RAM,
RAMOE(L) is low and RAMWE(L) is high. Both
RAMOE(L) and RAMWE(L) are low during a write to RAM.
8-257. During
an
110
port read/write,the Reamrite Decode logic decodes the address lines and the R/W(L)
line to determine
if
the I10 port is being read from or written to.
8-258. EXECUTIVE
AND
HP-IB 110. When a read I10 is taking place, the input buffer (U710 or U711) is
enabled and the output buffer
(U705 or U706) is placed into its high impedance state (OFF). For an write 110,
the input buffer is placed into its OFF state while the output buffer is enabled.
8-259.
OVEN OSCILLATOR MODULE (OPTION
01
0)
8-260. The Option 010 Oven Oscillator is an extremely stable, compact, low-power source of 10
MHz.
The crys-
tal, along with oscillator, circuit buffer amplifier, and oven control circuits are all mounted inside a thermally in-
sulated housing. A block diagram of the oven oscillator is shown in
Figire
8-7.
HP 5334B
-
Service Manual
8-33
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