HP 7475a - Page 63

Section VI
1-A-28-1
6-24
U11
+5V 24
12
13
22
19
18
15
A9
1 1
X•Y
U15 _
b-,..13
A1
21 2
OD
A2
20 4
A3
19 8
A4
18
A0-255
~+5V
16 VDD
A5
17
32
A6
16
64
AS
15
128
~
~G1
vss
G2
1411
10..r::::J 8.- G 3
~RAM r
07
07
9 9
06
S 2, A, 3 1, A, 3 S
06
7
2,A,3
1,A,3
7
05
05
2,A,3
1,A,3
6
04
6
2,A,3
1,A,3
04
5
03
03
5
2, A, 3
1, A, 3
4 02
02
4
2, A, 3 1, A, 3
3 3
01 01
2, A, 3
1, A, 3
2 2 09
09
2,A,3
1, A,3
Level of inputs in control block (S/R) deter-
mines direction of data flow.
Random access memory with 256 addresses
and 8-bit parallel inputs and outputs on the
same pins. Each data location is selected by
the 8-bit address in the upper left corner of
the control block. The data input (write)
function is enabled when gates G1/G2 are low
and G3 is true (pin 14 high, pin 10 low). The
read function when G1/G2 are high and G3 is
true.
Figure 6-23. ANSI Y32.14 Logic Symbols (Sheet 5 of 6)
Model 7475A