HP Compaq d330 DT User Manual

Technical Reference Guide
4.2.1 PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for
handling both address and data transfers. A bus transaction consists of an address cycle and one
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is
realized during burst modes in which a transaction with contiguous memory locations requires
that only one address cycle be conducted and subsequent data cycles are completed using auto-
incremented addressing. Four types of address cycles can take place on the PCI bus; I/O, memory,
configuration, and special. Address decoding is distributed (left up to each device on the PCI bus).
PC fig ress Register
I/O Port 0CF8h, R/W, (32-bit access only)
PCI Configuration Data Register
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
CFCh contains the configuration data.
Bit
Bit Function
31..0 Configuration Data.
7..2 pecifies config. reg.
1,0 cle Type ID.
I Con uration Add
Function
31 Configuration Enable
0 = Disabled
1 = Enable
ite 0s 30..24 Reserved - read/wr
23..16
15..11
Bus Number. Selects PCI bus
elects PCI PCI Device Number. S
device for access
ction of 10..8 Function Number. Selects fun
evice. selected PCI d
Register Index. S
Configuration Cy
4.2.1.1 I/O and Memory Cycles
essing
ucted a dword at a time with
ddressing assumed to increment accordingly (four bytes at a time).
4.2.1.2 Configuration Cycles
vice by
t 0CF8h holds a value that specifies the PCI bus, PCI
evice, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
00 = Type 0
01 = Type 1
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addr
is handled by the appropriate PCI device. For memory addressing, PCI devices decode the
AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linear-
incrementing) mode. In burst mode, subsequent data phases are cond
a
Devices on the PCI bus must comply with PCI protocol that allows configuration of that de
software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.3) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) a
d
0
hp compaq d330 and d530 Series of Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - June 2003
4-3

HP Compaq d330 DT Specifications

General

Brand	HP
Model	Compaq d330 DT
Category	Desktop
Language	English