Chapter 4 System Support
e
gure 4-8, 4-
yte block DnA is latched by the falling edge of AD_STBx while DnB is latched by the falling
dge of AD_STBx-. The signal level for AGP 8X transfers can be 0.8 or 1.5 VDC.
Figure 4-8. AGP 8X Data Transfer (Peak Transfer Rate: 2128 MB/s)
AGP 8X Transfers
The AGP 8X transfer rate allows 32 bytes of data to be transferred in one clock cycle. As with th
other transfer rates the 66-MHz CLK signal is used only for qualifying control signals while
strobe signals are used to latch each 4-byte transfer on the AD lines. As shown in Fi
b
e
A
T1
T2
1
s
Data
Latched
C
D
TRDY
D1A D2A D3A D1B D2B D3B D4A D4B
Final Data
Latched
_STBF
LK
AD
AD_STBS
hp compaq d330 and d530 Series of Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – June 2003
4-12