Technical Reference Guide
The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers.
4.4.2.1 DMA Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and works in
conjunction with the DMA controllers to define the complete (24-bit) address for the DMA
channels. Table 4-9 lists the page register port addresses.
Table 4-9. DMA Page Register Addresses
Table 4-9.
DMA Page Register Addresses
DMA Channel Page Register I/O Port
Controller 1 (byte transfers)
Ch 0
Ch 1
Ch 2
Ch 3
087h
083h
081h
082h
Controller 2 (word transfers)
Ch 4
Ch 5
Ch 6
Ch 7
n/a
08Bh
089h
08Ah
Refresh 08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel must be
programmed with 00h for proper operation.
The memory address is derived as follows:
24-Bit Address - Controller 1 (Byte Transfers)
8-Bit Page Register 8-Bit DMA Controller
A23..A16 A15..A00
ntrolle24-Bit Address - Co r 2 (Word Transfers)
Regist r er 8-Bit Page e 16-Bit DMA Controll
23..A17 A16..A01, (A00 = 0) A
Note that address line A16 from the DMA memory page register is disabled when DMA
controller 2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0
hen word-length transfers are selected. w
By not connecting A00, the following applies:
♦ can be moved or addressed is measured in 16-bits
♦ The words must always be addressed on an even boundary.
The size of the the block of data that
(words) rather than 8-bits (bytes).
hp compaq d330 and d530 Series of Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - June 2003
4-19