Chapter 5 Input/Output Interfaces
IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 5-1. EIDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82801, Device 31/Function 1)
PCI Conf.
Addr.
Register
Reset
Value
PCI Conf.
Addr.
Register
Reset
Value
00-01h Vender ID 8086h 0F..1Fh Reserved 0’s
02-03h Device ID [1] 20-23h BMIDE Base Address 1
04-05h PCI Command 0000h 2C, 2Dh Subsystem Vender ID 0000h
06-07h PCI Status 0280h 2E, 2Fh Subsystem ID 0000h
08h Revision ID 00h 30..3Fh Reserved 0’s
09h Programming 80h 40-43h Pri./Sec. IDE Timing 0’s
0Ah Sub-Class 01h 44h Slave IDE Timing 00h
0Bh Base Class Code 01h 48h Sync. DMA Control 00h
0Dh Master Latency Timer 00h 4A-4Bh Sync. DMA Timing 0000h
0Eh Header Type 00h 54h EIDE I/O Config.Register 00h
NOTE:
[1] ICH5 = 244Bh; ICH5 = 24CBh
IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
Table 5-2. IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
Size
(Bytes)
Register
Default
Value
00h 1 Bus Master IDE Command (Primary) 00h
02h 1 Bus Master IDE Status (Primary) 00h
04h 4 Bus Master IDE Descriptor Pointer (Pri.) 0000 0000h
08h 1 Bus Master IDE Command (Secondary) 00h
0Ah 2 Bus Master IDE Status (Secondary) 00h
0Ch 4 Bus Master IDE Descriptor Pointer (Sec.) 0000 0000h
NOTE:
Unspecified gaps are reserved, will return indeterminate data, and should not be written to.
5-2 hp compaq d330 and d530 Series of Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition – June 2003
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