Chapter 3. IBM System Storage DS4000 and DS5000 hardware 69
The optional dual-ported 8 Gbps Host Interface Card (HIC), shown in Figure 3-42, uses an
two port FC chip. This chip connects via PCI-E x8 to the XOR engine.
Figure 3-42 DS5020 Dual-Port 8 Gbps HIC architecture
If you have the iSCSI option, as shown in Figure 3-43, there is an QLogic top-off-engine
(TOE) build into the DS5020. It will be built in as a daughter card of the controller mainboard.
It reduces the workload of the controller CPU by calculating the whole Ethernet traffic and
transfers just the SCSI packet through it.
Figure 3-43 DS5020 iSCSI HIC architecture
Because of the similarities between the DS5000 controller models, we refer to 3.4.1, “DS5100
and DS5300 controller architecture” on page 31 for details about write cache, cache handling,
write operations, and cache block flow.
Power
Control
Logic
VPD
(8kB)
PMC QE8
Host I/F
SFP
SFP
8Gb/s
8Gb/s
PS_ENABLE
12C 2
12C 1
PCI-E x8
PCI-E I/F
FC Ports
VPD
(8kB)
QLogic EP4032
32KB
EEPROM
MAC1 MAC0
Dual GbE
iSCSI TOE
Power
Control
Logic
Host I/F
PS_ENABLE
PWR_GOOD
16K Config
EEPROM
(MAC Addr)
ZBT SSRAM
2MB
GMII
GMII
64b/133MHz PCI-XPCIe x4
PEX8114
PCI-X to PCIe
Bridge
12C 2
DDR Reassembly
Buffer
64MB + ECC
PHY0: 1Eh
100/1000
Ethernet
PHY1: 1Fh
100/1000
Ethernet
MDI
MDI
RJ45
RJ45
To Next Page
Loading...
Need help?
General