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Infineon TRAVEO T2G family CYT4D Series - 3.1.1 Use case; 3.1.2 Configuration

Infineon TRAVEO T2G family CYT4D Series
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Application Note 13 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the clock resources
3.1.1 Use case
Oscillator to use: Crystal unit
Fundamental frequency: 16 MHz
Maximum drive level: 300.0 µW
Equivalent series resistance: 150.0 ohm
Shunt capacitance: 0.530 pF
Parallel load capacitance: 8.000 pF
Crystal unit vendor’s recommended value of negative resistance: 1500 ohm
Automatic gain control: OFF
Note: These values are decided in consultation with the Crystal unit vendor.
3.1.2 Configuration
Table 1 lists the parameters and Table 2 lists the functions of the configuration part of in the SDL for ECO trim
settings.
Table 1 List of ECO trim settings parameters
Parameters
Description
Value
CLK_ECO_CONFIG2.WDTRIM
Watchdog trim
Calculated from Setting ECO parameters in
TRAVEO™ T2G user guide
7ul
CLK_ECO_CONFIG2.ATRIM
Amplitude trim
Calculated from Setting ECO parameters in
TRAVEO™ T2G user guide
0ul
CLK_ECO_CONFIG2.FTRIM
Filter trim of 3
rd
harmonic oscillation
Calculated from Setting ECO parameters in
TRAVEO™ T2G user guide
3ul
CLK_ECO_CONFIG2.RTRIM
Feedback resistor trim
Calculated from Setting ECO parameters in
TRAVEO™ T2G user guide
3ul
CLK_ECO_CONFIG2.GTRIM
Startup time of the gain trim
Calculated from Setting ECO parameters in
TRAVEO™ T2G user guide
3ul
CLK_ECO_CONFIG.AGC_EN
Automatic gain control (AGC) disabled
Calculated from Setting ECO parameters in
TRAVEO™ T2G user guide
0ul [OFF]
WAIT_FOR_STABILIZATION
Waiting for stabilization
10000ul
PLL_400M_0_PATH_NO
PLL number for PLL_400M_0
1ul
PLL_400M_1_PATH_NO
PLL number for PLL_400M_1
2ul
PLL_200M_0_PATH_NO
PLL number for PLL_200M_0
3ul
PLL_200M_1_PATH_NO
PLL number for PLL_200M_1
4ul
CLK_FREQ_ECO
Source clock frequency
16000000ul
SUM_LOAD_SHUNT_CAP_IN_PF
Sum of load shunt capacity (pF)
17ul