Infineon TRAVEO T2G family CYT4D Series - 3.1.3 Sample code for initial ECO configuration

Application Note 14 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the clock resources
Parameters
Description
Value
ESR_IN_OHM
Equivalent series resistance (ESR) (ohm)
250ul
MAX_DRIVE_LEVEL_IN_UW
Maximum drive level (uW)
100ul
MIN_NEG_RESISTANCE
Minimum negative resistance
5 * ESR_IN_OHM
Table 2 List of ECO trim settings functions
Functions
Description
Value
Cy_WDT_Disable()
Disable the watchdog timer
–
Cy_SysClk_FllDisable
Sequence(Wait Cycle)
Disable the FLL
Wait cycle =
WAIT_FOR_STABILIZATION
Cy_SysClk_Pll400M
Disable(PLL Number)
Disable the PLL400M_0
PLL number =
PLL_400M_0_PATH_NO
Disable the PLL400M_1
PLL number =
PLL_400M_1_PATH_NO
Cy_SysClk_PllDisable
(PLL Number)
Disable the PLL200M_0
PLL number =
PLL_200M_0_PATH_NO
Disable the PLL200M_1
PLL number =
PLL_200M_1_PATH_NO
AllClockConfiguration
()
Clock configuration
–
Cy_SysClk_EcoEnable
(Timeout value)
Set ECO enable and timeout value
Timeout value =
WAIT_FOR_STABILIZATION
Cy_SysLib_DelayUs(Wait
Time)
Delay by the specified number of
microseconds
Wait time = 1u (1us)
3.1.3 Sample code for initial ECO configuration
Code Listing 1 provides a sample code.
The following description will help you understand the register notation of the driver part of the SDL:
• SRSS->unCLK_ECO_CONFIG.stcField.u1ECO_EN is the SRSS_CLK_ECO_CONFIG.ECO_EN mentioned in the
Registers TRM. Other registers are also described in the same manner.
• Performance improvement measures
To improve the performance of register setting, the SDL writes a complete 32-bit data to the register. Each
bit field is generated in advance in a bit-writable buffer and written to the register as the final 32-bit data.
tempTrimEcoCtlReg.u32Register = SRSS->unCLK_ECO_CONFIG2.u32Register;
tempTrimEcoCtlReg.stcField.u3WDTRIM = wdtrim;
tempTrimEcoCtlReg.stcField.u4ATRIM = atrim;
tempTrimEcoCtlReg.stcField.u2FTRIM = ftrim;
tempTrimEcoCtlReg.stcField.u2RTRIM = rtrim;
tempTrimEcoCtlReg.stcField.u3GTRIM = gtrim;
SRSS->unCLK_ECO_CONFIG2.u32Register = tempTrimEcoCtlReg.u32Register;
See cyip_srss_v2.h under hdr/rev_x/ip for more information on the union and structure representation of
registers.