Infineon TRAVEO T2G family CYT4D Series - Page 15

Application Note 15 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the clock resources
Code Listing 1 General configuration of ECO settings
:
/** Wait time definition **/
#define WAIT_FOR_STABILIZATION (10000ul)
:
#define CLK_FREQ_ECO (16000000ul)
:
#define PLL_400M_0_PATH_NO (1ul)
#define PLL_400M_1_PATH_NO (2ul)
#define PLL_200M_0_PATH_NO (3ul)
#define PLL_200M_1_PATH_NO (4ul)
:
#define SUM_LOAD_SHUNT_CAP_IN_PF (17ul)
:
#define ESR_IN_OHM (250ul)
:
#define MIN_NEG_RESISTANCE (5 * ESR_IN_OHM)
#define MAX_DRIVE_LEVEL_IN_UW (100ul)
:
static void AllClockConfiguration(void);
:
int main(void)
{
/* disable watchdog timer */
Cy_WDT_Disable();
:
/* Disable Fll */
CY_ASSERT(Cy_SysClk_FllDisableSequence(WAIT_FOR_STABILIZATION) == CY_SYSCLK_SUCCESS);
/* Disable Pll */
CY_ASSERT(Cy_SysClk_Pll400MDisable(PLL_400M_0_PATH_NO) == CY_SYSCLK_SUCCESS);
CY_ASSERT(Cy_SysClk_Pll400MDisable(PLL_400M_1_PATH_NO) == CY_SYSCLK_SUCCESS);
CY_ASSERT(Cy_SysClk_PllDisable(PLL_200M_0_PATH_NO) == CY_SYSCLK_SUCCESS);
CY_ASSERT(Cy_SysClk_PllDisable(PLL_200M_1_PATH_NO) == CY_SYSCLK_SUCCESS);
/* Enable interrupt */
__enable_irq();
/* Set Clock Configuring registers */
AllClockConfiguration();
:
/* Please ensure output clock frequency using oscilloscope */
for(;;);
}
Code Listing 2 AllClockConfiguration() function
static void AllClockConfiguration(void)
{
:
/***** ECO setting ******/
cy_en_sysclk_status_t ecoStatus;
ecoStatus = Cy_SysClk_EcoConfigureWithMinRneg(
CLK_FREQ_ECO,
SUM_LOAD_SHUNT_CAP_IN_PF,
ESR_IN_OHM,
MAX_DRIVE_LEVEL_IN_UW,
MIN_NEG_RESISTANCE
);
CY_ASSERT(ecoStatus == CY_SYSCLK_SUCCESS);
{
SRSS->unCLK_ECO_CONFIG2.stcField.u3WDTRIM = 7ul;
SRSS->unCLK_ECO_CONFIG2.stcField.u4ATRIM = 0ul;
SRSS->unCLK_ECO_CONFIG2.stcField.u2FTRIM = 3ul;
SRSS->unCLK_ECO_CONFIG2.stcField.u2RTRIM = 3ul;
SRSS->unCLK_ECO_CONFIG2.stcField.u3GTRIM = 0ul;
SRSS->unCLK_ECO_CONFIG.stcField.u1AGC_EN = 0ul;
ecoStatus = Cy_SysClk_EcoEnable(WAIT_FOR_STABILIZATION);
CY_ASSERT(ecoStatus == CY_SYSCLK_SUCCESS);
}
:
return;
}
Either (1)-1 or (1)-2 can be used.
Comment out or delete unused code snippets in (1)-1 or (1)-2.
Define the TIMEOUT variable.
Define the oscillator parameters to use for software calculation.
Define the PLL number.
Watchdog timer disable
Disable the FLL.
Disable the PLL.
Trim and ECO setting. See Code Listing 2.
(1)-1. Trim settings for software calculation.
See Code Listing 4.
(1)-2. Trim settings according to the ECO user guide
ECO enable. See Code Listing 3.