Intel Agilex 7 FPGA I-Series - Page 44

Schematic Signal Name Description
SI5395_2_A_OEN_SYS_R
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
SI52204_PWRGD_R
TIED TO SYSTEM POWER OK
SI5395_2_A_IN_SEL0_R
DNU
SI5395_1_A_OEN_SYS_R
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
SI5391_A_OEN
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
SI5391_A_RSTN
LOW UNTIL SYSTEM POK
HIGH AFTER SYSTEM POK
SI5518_GPIO_0_R
DNU
CLK_OE_0_N
SI52204 CLK ENABLE0:
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
CLK_OE_1_N
SI52204 CLK ENABLE1:
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
CLK_OE_2_N
SI52204 CLK ENABLE2:
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
SI5518_GPIO_1_R
DNU
SI5518_GPIO_2_R
DNU
CLK_SI5395_2_FINC_R
DNU
CLK_SI5395_2_FDEC_R
DNU
CLK_SI5395_1_FINC_R
DNU
CLK_SI5395_1_FDEC_R
DNU
SI5518_I2C_R_EN
KEEP IT ENABLE:
LOW BEFORE SYSTEM POK
DNU AFTER POK
R_12A_SPARE_N
DRIVEN LOW
R_13A_SPARE_N
DRIVEN LOW
DIMM_IO_R_EN
ENABLE ALWAYS AFTER SYSTEM POK
LOW BEFORE SYSTEM POK
DNU AFTER SYSTEM POK
FMC_B_PCIE_PERSTN_3V3
DNU
FMC_B_PCIE_WAKEN_3V3
DNU
FMC_A_PCIE_WAKEN_3V3
DNU
FMC_A_PCIE_PERSTN_3V3
DNU
A. Development Kit Components
776646 | 2023.05.31
Intel Agilex
®
7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Guide
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