Intel Agilex 7 FPGA I-Series User Manual

Schematic Signal Name Description
SYS_LED3/D12
MAX_CONF_DONE for AVST configuration
SYS_LED5/D14
Reserved
SYS_LED7/D16
Reserved
SYS_PB0/S11
MAX_RESETn
SYS_PB1/S12
FPGA_RESETn
SYS_PB2/S14
Power recycle
SYS_PB3/S16
PGM_SEL for AVST configuration
SYS_PB4/S17
PGM_CFG for AVST configuration
FPGA_FAN_PWM
FAN 2 PWM SIGNAL
FPGA_FAN_TACH
FAN 2 TACHOMETER SIGNAL
QSFP_RIGHT_FAN_PWM
FAN 3 PWM SIGNAL
QSFP_RIGHT_FAN_TACH
FAN 3 TACHOMETER SIGNAL
QSFP_LEFT_FAN_PWM
FAN 1 PWM SIGNAL
QSFP_LEFT_FAN_TACH
FAN 1 TACHOMETER SIGNAL
CORE_FETS_FAN_PWM
FAN 0 PWM SIGNAL
CORE_FETS_FAN_TACH
FAN 0 TACHOMETER SIGNAL
MUX_SEL0
MUX SELECT FOR CHOOSING EITHER REFCLK_FGT_12A_8_DP/N (OR)
REFCLK_FGT_12A_9_DP/N FOR FMCA_RECRD_CLK 0: FMCA_RECRD_CLK=
REFCLK_FGT_12A_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_12A_9_DP/N
MUX_SEL1
MUX SELECT FOR CHOOSING EITHER REFCLK_FGT_13C_8_DP/N (OR)
REFCLK_FGT_13C_9_DP/N FOR FMCB_RECRD_CLK 0: FMCA_RECRD_CLK=
REFCLK_FGT_13C_8_DP/N 1: FMCA_RECRD_CLK= REFCLK_FGT_13C_9_DP/N
MCIO_CLK_SEL_EP_N
TIED TO MUX_DIP_SW2
MCIO_CLK_ENN
TIED TO MUX_DIP_SW3
MUX_DIP_SW0
DIP SWITCH 0 SIGNAL (by default high)—tie this to MUX_SEL0
MUX_DIP_SW1
DIP SWITCH 1 SIGNAL (by default high)—tie this to MUX_SEL1
MUX_DIP_SW2
MCIO_CLK_SEL_EP_NN:
LOW BEFORE SYSTEM POK
HIGH AFTER SYSTEM POK
MUX_DIP_SW3
MCIO_CLK_ENN:
HIGH BEFORE SYSTEM POK
LOW AFTER SYSTEM POK
VCCL_I2C_EN
CONNECT VCCL_SCL/SDA TO SYSTEM Intel MAX 10 (DEFAULT ENABLE-1)
R_13C_PERST_IO_N
DRIVEN LOW
R_13B_PERST_IO_N
TIED TO MCIO PREST INTERNALLY
R_12B_PERST_IO_N
DRIVEN LOW
R_12C_PERST_IO_N
DRIVEN LOW
SI5395_1_A_IN_SEL0_R
DNU
continued...
A. Development Kit Components
776646 | 2023.05.31
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Intel Agilex
®
7 FPGA I-Series Transceiver (6 × F-Tile) Development Kit User
Guide
43

Intel Agilex 7 FPGA I-Series Specifications

General

Brand	Intel
Model	Agilex 7 FPGA I-Series
Category	Microcontrollers
Language	English