Intel® Server Board S2400SC TPS Functional Architecture
Revision 2.0 Intel order number G36516-002 23
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device. Independent channel mode supports x4 SDDC. x8 SDDC requires
lockstep mode
o Lockstep mode where channels 0 & 1 and channels 2 & 3 are operated in
lockstep mode
o Data scrambling with address to ease detection of write errors to an incorrect
address.
o Error reporting from the Machine Check Architecture
o Read Retry during CRC error handling checks by iMC
o Channel mirroring within a socket
- CPU1 Channel Mirror Pairs B and C
- CPU2 Channel Mirror Pairs E and F
o Error Containment Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature
3.2.2.1 Supported Memory
Table 4. UDIMM Support Guidelines
Ranks
Per
DIMM &
Data
Width
Memory Capacity Per DIMM1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3
Non-
1GB 2GB 4GB n/a 1066, 1333, n/a 1066, 1333 n/a 1066
Non-
2GB 4GB 8GB n/a 1066, 1333, n/a 1066, 1333 n/a 1066
SRx16
Non-
512MB 1GB 2GB n/a 1066, 1333, n/a 1066, 1333 n/a 1066
1GB 2GB 4GB
1066, 1333,
1066, 1333 1066 1066
2GB 4GB 8GB
1066, 1333,
1066, 1333 1066 1066
Notes:
1. Supported DRAM Densities are 1Gb, 2Gb and 4Gb. Only 2Gb and 4Gb are validated by Intel.
2. Command Address Timing is 1N for 1DPC and 2N for 2DPC.
3. For Memory Population Rules, please refer to the Romley Platform Design Guide.
Supported and Validated
Supported but not Validated
To Next Page
Loading...
Need help?
General
