Functional Architecture Intel® Server Board S2400SC TPS
24 Intel order number G36516-002 Revision 2.0
Table 5. RDIMM Support Guidelines
Ranks Per
DIMM &
Data
Width
Memory Capacity Per DIMM1
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3
SRx8 1GB 2GB 4GB 1066 1333
1066 1333
1066 1333
DRx8 2GB 4GB 8GB 1066 1333
1066 1333
1066 1333
1066 1333
1066 1333
1066 1333
SRx4 2GB 4GB 8GB 1066 1333
1066 1333
1066 1333
1066 1333
1066 1333
1066 1333
DRx4 4GB 8GB 16GB 1066 1333
1066 1333
1066 1333
Notes:
1. Supported DRAM Densities are 1Gb, 2Gb and 4Gb. Only 2Gb and 4Gb are validated by Intel.
2. Command Address Timing is 1N.
3. For Memory Population Rules, please refer to the Romley Platform Design Guide.
Supported and Validated
Supported but not Validated
3.2.2.2 Memory population rules
Note: Although mixed DIMM configurations may be functional, Intel only performs platform
validation on systems that are configured with identical DIMMs installed.
Each processor provides three channels of memory, each capable of supporting up to two
DIMMs.
DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
The memory channels from processor socket 1 are identified as Channel A, B and C.
The memory channels from processor socket 2 are identified as Channel D, E and F.
The silk screened DIMM slot identifiers on the board provide information about the
channel, and therefore the processor to which they belong. For example, DIMM_A1 is
the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM socket on
Channel D on processor 2.
The memory slots associated with a given processor are unavailable if the
corresponding processor socket is not populated.
A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory.
In this case, the memory is
shared by the processors.
However, the platform suffers performance degradation and
latency due to the remote memory.
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