Intel Xeon E5-2600 Series - Page 54

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
54 Reference Number: 327043-001
REQUESTS
• Title: Read and Write Requests
• Category: REQUESTS Events
• Event Code: 0x01
• Max. Inc/Cyc: 1, Register Restrictions: 0-3
• Definition: Counts the total number of read requests made into the Home Agent. Reads include all
read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).
RPQ_CYCLES_NO_REG_CREDITS
• Title: iMC RPQ Credits Empty - Regular
• Category: RPQ_CREDITS Events
• Event Code: 0x15
• Max. Inc/Cyc: 4, Register Restrictions: 0-3
• Definition: Counts the number of cycles when there are no "regular" credits available for posting
reads from the HA into the iMC. In order to send reads into the memory controller, the HA must
first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular
credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This
count only tracks the regular credits Common high banwidth workloads should be able to make use
of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular
and special buffers at the same time. One can filter based on the memory controller channel. One
or more channels can be tracked at a given time.
Table 2-47. Unit Masks for IMC_WRITES
Extension
umask
[15:8]
Description
FULL bxxxxxxx1 Full Line Non-ISOCH
PARTIAL bxxxxxx1x Partial Non-ISOCH
FULL_ISOCH bxxxxx1xx ISOCH Full Line
PARTIAL_ISOCH bxxxx1xxx ISOCH Partial
ALL b00001111 All Writes
Table 2-48. Unit Masks for REQUESTS
Extension
umask
[15:8]
Description
READS b00000011 Reads:
Incoming ead requests. This is a good proxy for LLC Read Misses
(including RFOs).
WRITES b00001100 Writes:
Incoming write requests.
Table 2-49. Unit Masks for RPQ_CYCLES_NO_REG_CREDITS
Extension
umask
[15:8]
Description
CHN0 bxxxxxxx1 Channel 0:
Filter for memory controller channel 0 only.
CHN1 bxxxxxx1x Channel 1:
Filter for memory controller channel 1 only.
CHN2 bxxxxx1xx Channel 2:
Filter for memory controller channel 2 only.
CHN3 bxxxx1xxx Channel 3:
Filter for memory controller channel 3 only.