IEEE-488 Reference
5-13
(1). When the unmasked bit of the Arm Event Register sets,
it is ANDed with the corresponding set bit in the Arm Event
Enable Register. The logic “1” output of the AND gate is ap-
plied to the input or the OR gate and thus, will set the Waiting
for Arm bit in the Operation Condition Register.
Bit B1 of the Arm Event Enable Register can be set or
cleared by using the following SCPI command:
:STATus:OPERation:ARM:ENABle <NRf>
The following SCPI query command can be used to read the
Arm Event Enable Register:
:STATus:OPERation:ARM:ENABle?
Reading this register using the above SCPI command will
not clear the register. The following list summarizes opera-
tions that will clear the Arm Event Enable Register:
1. Cycling power.
2. Sending the :STATus:OPERation:ARM:ENABle 0
command.
5.6.4 Sequence event status
The reporting of sequence events is controlled by a set of 16-
bit registers; the Sequence Condition Register, the Transition
Filter, the Sequence Event Register and the Sequence Event
Enable Register. Figure 5-9 shows how these registers are
structured.
Two bits of this register set are used by the Model 7001 to re-
port sequence events. Bit B1 (In Arm Layer 1) is set when in-
strument is in (or exited) the arm layer (Arm Layer 1) of
operation. Bit B2 (In Arm Layer 2) is set when the instru-
ment is in (or exited) the scan layer (Arm Layer 2). The op-
eration process over the bus is explained in paragraph 5.7.
The various registers used for sequence event status are de-
scribed as follows. Note that these registers are controlled by
the :STATus:OPERation:ARM:SEQuence commands of the
:STATus subsystem (see paragraph 5.16).
Sequence Condition Register —
This is a real-time 16-bit
read-only register that constantly updates to reflect the cur-
rent arm layer status of the instrument. For example, if the
Model 7001 is currently in the scan layer of operation, bit B2
(In Arm Layer 2) of this register will be set.
The following SCPI query command can be used to read the
Sequence Condition Register:
:STATus:OPERation:ARM:SEQuence:CONDition?
The Sequence Condition Register and the Transition Filter
are used to set the bits of the Sequence Event Register. The
Transition Filter is discussed next.
Sequence Transition Filter —
The transition filter is made
up of two 16-bit registers that are programmed by the user. It
is used to specify which transition (0 to 1, or 1 to 0) in the
Sequence Condition Register will set the corresponding bit
in the Sequence Event Register.
The filter can be programmed for positive transitions (PTR),
negative transitions (NTR) or both. When an event bit is pro-
grammed for a positive transition, the event bit in the Se-
quence Event Register will set when the corresponding bit in
the Sequence Condition Register changes from 0 to 1. Con-
versely, when programmed for a negative transition, the bit
in the status register will set when the corresponding bit in
the condition register changes from 1 to 0.
The transition filter registers can be set or cleared by using
the following SCPI commands:
:STATus:OPERation:ARM:SEQuence:PTRansition <NRf>
:STATus:OPERation:ARM:SEQuence:NTRansition <NRf>
The transition filter registers can be read at any time by using
the following SCPI query commands:
:STATus:OPERation:ARM:SEQuence:PTRansition?
:STATus:OPERation:ARM:SEQuence:NTRansition?
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