Theory of Operation
6-5
6.4 Relay control circuitry
The relay control circuits collectively reside on the
backplane card and each relay or matrix card assembly
plugged into the Model 7001 mainframe.
The backplane board acts as a passive conduit for:
• Control signals from the digital board to the switch
cards.
• Responses from the switch cards to the digital
board.
• Power lines to the cards.
• Expansion of analog signals among the cards.
• Incorporation of relay drivers for the Model 705/
706 switch cards.
The following paragraphs describe operation of the re-
lay control circuitry on the digital board, as well as a
typical matrix card. Also refer to backplane board sche-
matic 7011-176.
6.4.1 Backplane interface
For the following discussion, consult Figures 6-3 and 6-
4, which show a simplified schematic and timing dia-
gram for the backplane interface.
During power-up, the main microprocessor reads card
identification data via the backplane interface from the
EEPROM on each switch card installed in the main-
frame. The microprocessor also sends relay control
data to the switch cards during the course of normal
operation. The data is sent and received in serial form.
The serial data from the microprocessor has a common
relay clock, ID clock, and relay data line that is multi-
plexed between the mainframe’s slot 1 and slot 2 before
being sent to the backplane. The multiplexing is con-
trolled by line PB6 and PB6
. The remaining lines from
the 68302 are buffered before terminating to the back-
plane interface.
At the start of a WRITE to a switch card, the 68302 in-
ternal registers are loaded with 5 bytes of information.
PB6 is set to talk either to slot 1 or slot 2. The data is
loaded on 40 clock cycles. At completion, the appropri-
ate strobe line will go high and return low, latching the
data into the backplane drivers and (if installed) the
switch card drivers. On the first WRITE to the switch
card, the enable line will go low, enabling the data in
the register to be present on the output.
To start a READ cycle of a switch card, the user must be
in the “CARD
→
READ-I/O-CARD” menu. This ini-
tializes the 68302 to allocate memory space to store I/
O data. When in this menu, the STROBE signal will go
high and return low, latching in data from the parallel-
to-serial input register. Then, R/W
and CS will be en-
abled along with 40 clock cycles, which are needed to
read the I/O data. The ENABLE line will be active low
after the first strobe pulse.
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