88 Chapter 3
Theory of Operation
Multiple Module Synchronization
external Sample clock can be in the range of 625 MHz to 1.25 GHz. The Sample
clock provides the final retiming of the analog output from each AWG. Any skew in
the Sample clock cable delays between the multiple modules will result in the same
skew in the analog outputs. Typically, the sample clock signal is split with a
matched passive splitter and the cable lengths are matched to better than 5 mm. The
resulting skew is small and repeatable. The skew can be measured and calibrated,
along with any phase shifts in cables on the ARB outputs, by adding fixed delay
offsets to the AWG waveforms. The SYNC clock is used internal to the AWG to
clock the internal data generator and to clock in the synchronous triggers. When
using the internal clock, the SYNC clock has a frequency of 1/8 of the sample clock
rate (156.25 MHz). When synchronizing multiple units, the SYNC clock output
must be enabled in software (in the Master) and the external SYNC clock input
selected in all the modules. The SYNC clock signal is split passively and distributed
with low skew. The SYNC clock output level and the input sensitivity support up to
a 1 to 8 split (fan-out) using matched 50 Ohm splitters (6 dB loss per 1 to 2 splitter).
There is a specific SYNC cable length that is required as a function of the Sample
clock frequency. Several different lengths can be used, provided they are integer
multiples of one half of a SYNC clock period.
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