96 Chapter 4
Dynamic Sequencing Option 300
Dynamic Sequencing
Signal Levels
All pins are configured as 2.5 V, LVCMOS inputs. The logic levels must be
within the following ranges:
Low −0.2 to +0.5 V
High +2.0 to +2.8 V
Signal Descriptions
Data Input
The input data represents a handle to the next scenario to be played by the
AWG module. Only the first 8,192 scenarios are available. The scenario
handle must be divided by 2 before being written to the AUX port. For
example, to play the scenario with a handle of 72, write the value 36 to the
AUX port. All scenario handles are even numbers.
Data Valid
When Data Valid is asserted high, it indicates that the data present on the
Data pins is valid and can be latched into the channel 1 and channel 2 next
sequence register.
Trigger
Trigger input can be configured to be either rising-or falling-edge, with a
programmable delay. Refer to “Triggers” on page 80.
NOTE The latency between trigger assertion and sequence playback is the same as
that for the front panel trigger inputs, a resolution of one SYNC clock.
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