Instrument Status 8
Keysight 53210A User’s Guide 227
Status Byte Register
The Status Byte register contains the summary bits of the Questionable Data
Register Group, the Standard Operation Register Group, the Standard Event
Register, the counter error queue, and the output buffer (Figure 8-1).
The Master Summary RQS bit (Bit 6) is set (1) when any other bit in the Status
Byte register is set.
Reading the Status Byte Register
The Status Byte register is read with either of the following commands:
*STB?
SPOLL
Both commands return the decimal weighted sum of all set bits in the register.
The difference between the commands is that
*STB? does not clear bit 6 (RQS).
The serial poll (SPOLL) does clear bit 6.
All bits in the Status Byte register (except bit 4) are cleared with the command:
*CLS
Bit 4 is cleared when data is read from the output buffer.
Service Request Enable Register
The Service Request Enable register specifies which (status group) summary bit(s)
will send a service request message to the computer.
The bits are specified with the command:
*SRE <enable>
*SRE? (query form)
– enable: decimal value corresponding to the binary-weighted sum of the bits in
the register. For example, to enable the bit representing the Questionable Data
Register Group:
*SRE 8.
Chapter 7 and Product Reference CD (p/n 53220-13601) contain examples using
the
STATus subsystem.
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