1Overview
38 Keysight E6961A User Guide and Method of Implementation
Transmitter Distortion Tests Information
When operating in Test Mode 4 and capturing the waveform using the Section 11
of the fixture, the peak distortion shall be less than 15 mV.
Reference [1] specifies that the peak distortion is determined by sampling the
differential signal output with the symbol rate clock at an arbitrary phase and
processing a block of any 2047 consecutive samples with MATLAB code in
reference [1].
A software high pass filter is applied to the sampled signal before
post-processing.
Alternatively, this test can also be run without the disturbing signal, but the result
cannot be used to determine compliance.
Transmitter Distortion Enhance Clock Recovery Algorithm
Keysight employs an enhanced clock recovery algorithm when the TX_TCLK is not
available. The algorithm conditions the signal to the nominal bitrate. This is
enabled by default when the Use 10MHz Ref Clock checkbox is disabled.
When the Use 10MHz Ref Clock checkbox is enabled, the E6960-66600
Frequency Divider board as well as access to TX_TCLK is required for
synchronization.
If using the Frequency Divider, connect the 10 MHz output(s) of the divider to
the 10 MHz Ref In Input of the oscilloscope and function generator for clock
synchronization.
This test can only be run using a differential output from the transmitter (MDI).
Refer to “General Test Setup” on page 14 for connection details. A differential
probe cannot be used for this test.
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