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Mitsubishi Electric MELSEC iQ-R-R6SFM - Page 856

Mitsubishi Electric MELSEC iQ-R-R6SFM
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854
APPX
Appendix 5 List of Special Register Areas
SD622 Data memory (drive
4) capacity
Data memory (drive
4) capacity: the lower
digits (unit: K bytes)
The capacity of the data memory is stored in increments of 1K byte
(the amount of free space for a formatted memory card is stored).
S (Initial) ALL
SD623 Data memory (drive
4) capacity: the higher
digits (unit: K bytes)
The capacity of the data memory is stored in increments of 1K byte
(the amount of free space for a formatted memory card is stored).
S (Initial) ALL
SD626 Extended SRAM
cassette capacity
identification
information
Capacity identification
information of the
Extended SRAM
cassette
Capacity identification information of the Extended SRAM cassette
is stored.
Unmounted: 0, 1M: 1, 2M: 2, 4M: 3, 8M: 4, 16M: 5
S (Initial) ALL
*5
SD629 Program memory
write (transfer) status
Write (transfer) status
display
(percent)
This register displays write (transfer) status to the program memory
in percentage (0 to 100%). The initial value is "0". Upon completion
of writing, this register is set to "100". It is set to "0" at the time
when the write command is issued.
S (Writing) ALL
SD630 Program memory
write count index
Index of the number
of write operations up
to now
This register indicates the index value for the number of write
operations to the program memory up to now (stored as a 32-bit
BIN value). However, the number of write operations is not equal
to the index value.
When the index value exceeds 100000, an error is generated
(the index value is continued to be counted even when it exceeds
100000). If the index value exceeds 100000, the CPU module
must be replaced.
S (Writing) ALL
SD631 ALL
SD633 Data memory write
(transfer) status
Write (transfer) status
display
(percent)
This register displays write (transfer) status to the data memory in
percentage. (0 to 100%). The initial value is "0". Upon completion of
writing, this register is set to "100". It is set to "0" at the time when
the write command is issued.
*2
S (Writing) ALL
SD634 Index for the number
of data memory write
operations
Index of the number
of write operations up
to now
This register indicates the index value for the number of write
operations to the data memory up to now (stored as a 32-bit BIN
value). However, the number of write operations is not equal to
the index value.
When the index value exceeds 100000, an error is generated
(the index value is continued to be counted even when it exceeds
100000). If the index value exceeds 100000, the CPU module
must be replaced.
S (Writing) ALL
SD635 ALL
SD638 Index for the number
of system memory
write operations
Index of the number
of write operations up
to now
This register indicates the index value for the number of write
operations to the system memory (Flash ROM)
*3
up to now.
(stored as a 32-bit BIN value). However, the number of write
operations is not equal to the index value.
When the index value exceeds 100000, an error is generated
(the index value is continued to be counted even when it exceeds
100000). If the index value exceeds 100000, the CPU module
must be replaced.
S (Writing) RnPSF
RnSF
SD639 RnPSF
RnSF
SD640 Internal buffer empty
area usage status
Internal buffer empty
area usage status
(usage status of the
internal buffer for
functions where the
internal buffer
capacity is not set in
the internal buffer
capacity setting of the
CPU parameters)
This register stores the following in a bit pattern: usage status of the
internal buffer for functions where the internal buffer capacity is not
set in the internal buffer capacity setting of the CPU parameters.
(On indicates being used.)
b0: Used for realtime monitor
b1 to b15: Not used
S (Status
change)
Rn
SD642 Internal buffer
capacity
Internal buffer
capacity
Low-order (in K
bytes)
The capacity of the internal buffer is stored in K bytes. S (Initial) Rn
SD643 Internal buffer
capacity
High-order (in K
bytes)
The capacity of the internal buffer is stored in K bytes. S (Initial) Rn
No. Name Data stored Details Set by
(setting
timing)
CPU

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