Mitsubishi MELSEC-Q/L

17
CHAPTER 11 REDUNDANT SYSTEM INSTRUCTIONS (For REDUNDANT CPU) 703
11.1 SP.CONTSW System Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703
APPENDICES 706
Appendix 1 OPERATION PROCESSING TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Appendix 1.1 Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .706
Appendix 1.2 Operation Processing Time of Basic Model QCPU . . . . . . . . . . . . . . . . . . . . . . . . .707
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/
Redundant CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .722
Appendix 1.4 Operation Processing Time of Universal Model QCPU . . . . . . . . . . . . . . . . . . . . . .746
Appendix 1.4.1 Subset instruction processing time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .746
Appendix 1.4.2 Processing time of instructions other than subset instruction . . . . . . . . . . . . . .759
Appendix 1.5 Operation Processing Time of LCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .802
Appendix 1.5.1 Subset instruction processing time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .802
Appendix 1.5.2 Processing time of instructions other than subset instruction . . . . . . . . . . . . . .808
Appendix 2 CPU PERFORMANCE COMPARISON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Appendix 2.1 Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU . . . . . . . . . . . . . .826
Appendix 2.1.1 Usable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .826
Appendix 2.1.2 I/O control mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .827
Appendix 2.1.3 Data that can be used by instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .828
Appendix 2.1.4 Timer comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .829
Appendix 2.1.5 Comparison of counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .830
Appendix 2.1.6 Comparison of display instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .830
Appendix 2.1.7 Instructions whose designation format has been changed
(Except dedicated instructions for AnACPU and AnUCPU) . . . . . . . . . . . . . . . .831
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions. . . . . . . . . . . . . . . . . . . . . . . . . .832
Appendix 3 APPLICATION PROGRAM EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Appendix 3.1 Concept of Programs which Perform Operations of a nth power of X, a nth root X
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .833
INDEX 834
INSTRUCTION INDEX 839
WARRANTY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843