-
CR102, biasing them to a low-impedance state. Bias current returns to
ground through U504 pin 20. In receive, U504 pin 21 is pulled down
to ground and pin 20 is pulled up to B+, reverse biasing diodes CR104
and CR102 to a high impedance.
Receiver Front End For the purposes of this discussion, the receiver front end is defined to
be the circuitry from the antenna switch to the output of the IF crystal
filter. The 800MHz front end is designed to convert the received RF
signal to the 1st IF frequency of 73.35MHz, while at the same time
providing for spurious immunity and adjacent channel selectivity. A
review of the interstage components of the front end will now be
presented with emphasis on troubleshooting considerations.
The received RF signal is passed through the antenna switch input
matching components C101, L105, and C114 tank components C106
and L103 (which are anti-resonant at the radios transmitter
frequencies), and output matching components C103 and L104. Both
pin diodes CR102 and CR104 must be back biased to properly route
the received signal.
The stage following the antenna switch is a 50-ohm, inter-digitated, 3-
pole, stripline preselector (U201). The preselector is positioned after
the antenna switch to provide the receiver preamp some protection to
strong signal, out-of-band signals.
After the preselector (U201), the received signal is processed through
the receiver preamp, U202. The preamp is a dual-gate GaAs MESFET
transistor which has been internally biased for optimum IM, NF, and
gain performance. Components L201 and L202 match the input (gate
1) of the amp to the first preselector, while at the same time
connecting gate 1 to ground potential. The output (drain) of the amp
is pin 3 and is matched to the subsequent receiver stage via
components L204, C205 and C222. A supply voltage of 5Vdc is
provided to pin 3 via an RF choke L203 and bypass C204. The 5 volt
supply is also present at pin 4 which connects to a voltage divider
network that biases gate 2 (pin 5) to a predefined quiescent voltage of
1.2Vdc. Resistor R202 and capacitor C203 are connected to pin 5 to
provide amp stability. The FET source (pin 7) is internally biased at
0.55 to 0.7Vdc for proper operation with bypass capacitors C201 and
C202 connected to the same node.
The output of the amp is matched to a second 3-pole preselector
(U203) of the type previously discussed. The subsequent stage in the
receiver chain is the 1st mixer U205, which uses low-side injection to
convert the RF carrier to an intermediate frequency (IF) of 73.35MHz.
Since low-side injection is used, the LO frequency is offset below the
RF carrier by 73.35MHz, or Flo = Frf - 73.35MHz. The mixer utilizes
GaAs FETs in a double balanced Gilbert Cell configuration. The LO
port (pin 8) incorporates an internal buffer and a phase shift network
to eliminate the need for a LO transformer. The LO buffer bypass
capacitors (C208, C221, and C216) are connected to pin 10 of U205,
and should exhibit a nominal dc voltage of 1.2 to 1.4Vdc. Pin 11 of
U205 is LO buffer Vdd (5Vdc) with associated bypass capacitors C226
and C209 connected to the same node. An internal voltage divider
network within the LO buffer is bypassed to virtual ground at pin 12
To Next Page
Loading...
Need help?
General
