-
program code contains the interrupt vectors and the reset vector and
is basically an expanded bootstrap code. When the MCU messages the
DSP that the ADSIC has been configured, the DSP overlays more code
from the ROM into external SRAM and begins to execute it. Overlays
occur at different times when the DSP moves code from the ROM into
external SRAM depending on immediate mode of operation, such as
changing from transmit to receive.
MCU System Clock The MCU (U204) system clock is provided by circuitry internal to the
MCU and is based on the crystal reference, Y201. The nominal
operating frequency is 7.3728MHz. This signal is available as a clock at
4XECLK on U204 and is provided to the SLIC (U206) for internal clock
timing. The MCU actually operates at a clock rate of 1/4 the crystal
reference frequency or 1.8432MHz. This clock is available at ECLK on
U204.
The MCU clock contains a crystal warp circuit comprised of L201,
Q205, and C228. This circuit is controlled by an I/O port (PA6) on the
MCU. This circuit moves the operating frequency of the oscillator
about 250ppM on certain receive channels to prevent interference
from the MCU bus noise.
DSP System Clock The DSP (U405) system clock, DCLK, is provided by the ADSIC (U406).
It is based off the crystal reference, Y401, with a nominal operating
frequency of 33.0000MHz. ADSIC contains an internal clock divider
circuit which can divide the system clock from 33MHz to 16.5 or
8.25MHz operation. The DSP controls this divider by writing to the
ADSIC parallel registers. This frequency is determined by the processes
the DSP is running and is generally configured to the slowest operating
speed possible to reduce system power consumption.
The additional circuitry of CR402, L403, C459, C467, C491, and C490
make up a crystal warp circuit. This circuit is controlled by the OSCw
signal from ADSIC which is configured by the host through the SPI
bus. This circuit moves the operating frequency of the oscillator about
400ppM on certain receive channels to prevent interference from the
DSP bus noise.
Radio
Power-Up/
Power-Down
Sequence
Radio power-up begins when the user closes the radio on/off switch on
the control top. This enables 7.5Vdc on the B+_SENSE signal. This
signal enables the pass element Q207 through Q206 enabling SW_B+
to the VOCON board and transceiver board. B+_SENSE also enables
the +5Vdc regulator U409. When +5Vdc has been established, it is
sensed by the supervisory IC U407. U407 disables the system reset
through the delay circuit R481 and C482.
When the MCU comes out of reset, it fetches the reset vector in ROM
at $FFFE, $FFFF and begins to execute the code this vector points to. It
configures the SLIC through the parallel bus registers. Among other
things it enables the correct memory map for the MCU. It configures
all the transceiver devices on the SPI bus. The MCU then pulls the
ADSIC out of reset and after a minimal delay the DSP also. It then
configures the ADSIC through the SPI bus configuring among other
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