-
S902 is a binary coded switch. The output pins from this switch are
connected to I/O ports on the controller. It provides a 4 bit binary
word to the MCU indicating which of the 16 positions the rotary is set
to. This switch provides an additional output, A/B_SWITCH, which
effectively doubles its range by providing decoding for two sets of 16
positions. A/B_SWITCH is also read by the MCU on an I/O port.
Controller Memory
Map
Figure 12 depicts the controller section memory map for the parallel
data bus as used in normal modes of operation. There are three maps
available for normal operation, but map 2 is the only one used. In
bootstrap mode, the mapping is slightly different and will be
addressed later.
The external bus for the host controller (U204)) consists of one 32Kx8
SRAM (U202), one 32Kx8 EEPROM (U201), two 256Kx8 FLASH ROMs
(U205, U210), and SLIC (U206) configuration registers. In addition the
DSP host port is mapped into this bus through the SLIC address space.
The purpose of this bus is to interface the MCU (U204) to these
devices.
The MCU executes program code stored in the FLASH ROMs. On a
power-up reset, it fetches a vector from $FFFE, $FFFF in the ROMs and
begins to execute code stored at this location. The external SRAM
along with the internal 1Kx8 SRAM is used for temporary variable
storage and stack space. The internal 512 bytes of EEPROM along with
the external EEPROM are used for non volatile storage of customer
specific information. More specifically the internal EEPROM space
contains transceiver board tuning information and on power-down
some radio state information is stored in the external EEPROM.
The SLIC is controlled through sixteen registers mapped into the MCU
memory at $1400 - $14FF. This mapping is achieved by the following
signals from the MCU: R/W*, CSIO1*, HA0-HA4,HA8, HA9. Upon
power-up, the MCU configures the SLIC including the memory map
by writing to these registers.
The SLIC memory management functions in conjunction with the
chip selects provided by the MCU provide the decoding logic for the
memory map which is dependent upon the “map” selected in the
SLIC. The MCU provides a chip select, CSGEN*, which decodes the
valid range for the external SRAM. In addition CSI01* and CSPROG*
are provide to the SLIC decoding logic for the external EEPROM and
FLASH ROM respectively. The SLIC provides a chip select and banking
scheme for the EEPROM and FLASH ROM. The FLASH ROM is banked
into the map in 16KB blocks with one 32KB common ROM block. The
external EEPROM may be swapped into one of the banked ROM areas.
This is all controlled by EE1CS*, ROM1CS*, ROM2CS*, HA14_OUT,
HA15_OUT, HA16, and HA17 from the SLIC (U206) and D0-D8 and
A0-16 from the MCU (U204).
The SLIC provides three peripheral chip selects; XTSC1B, XTCS2B, and
XTCS3B. These can be configure to drive an external chip select when
it's range of memory is addressed. XTSC1B is used to address the host
port interface to the DSP. XTSC2B is used to address a small portion of
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