3.6
MC68705R3 and MC68705R5 MEMORY
MAP
The memory maps for the MC68705R3 and MC68705R5 are shown in Figure 3-6 and are identical
to
the
MC68705U3 and MC68705U5 except
that
two
additional registers, the analog-to-digital control
register and the analog-to-digital result register have been added
at
locations
$OOE
and
$OOF,
respectively.
The
MC68705U3/MC68705U5 and MC68705R3/MC68705R5 are intended
to
exactly emulate the
MC6805U3 and MC6805R3 respectively.
o
7 6 5 4
321
0
1/0 Ports
$000
0
Port A Data Register
Timer
1
Port B Data Register
RAM
(128 Bytes)
$07F
2
Port C Data Register
Page Zero
$080
3
Port D Data Register
User EPROM
\OFF
(128 Bytes)
4
PortA
DDR*
~------
$100
5
Port B
DDR*
User
6
PortC
DDR*
Main
7
Not
Used
EPROM
8
Timer Data Register
(3640 Bytes)
9
Timer Control
Regi~ter
3895
3896
3897
3967
$F37
10
Miscellaneous Register
1--------
$F38
Mask Option Register
11
Program Control Register
$F39
Not
Used
Not
Used
$F7F
12
3968
Bootstrap
$F80
13
Not
Used
ROM
4087
(120 Bytes)
$FF7
14
AI
D Control Register
4088
4089
4090
Interrupt
4091
Vectors
4092
4093
4094
4095
$FF8
15
AI
D Register
Timer Interrupt
~------
$FF9
$FFA
16
RAM
External Interrupt
$FFB
(112 Bytes)
~-
-
--
--
$FFC
SWI
$FFD
Stack
~-
---
--
$FFE
(31
Bytes Maximum)
Reset
$FFF
t
127
* Caution: Data direction registers (DDRs) are write-only; they read
as
$FF.
Figure 3-6. MC68705R3 and MC68705R5
Memory
Map
3-6
$000
$001
$002
$003
$004*
$005*
$006*
$007
$008
$009
$OOA
$OOB
$OOC
$ooD
$OOE
$OOF
$010
$07F
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