NEC switch - Receive Bank Switching ID Detection Buffer Operation; Flowchart of Receive Bank Switching ID Detection Buffer Operation

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CHAPTER 8 USB FUNCTION

User’s Manual U12978EJ3V0UD

147

8.8.2 Receive bank switching ID detection buffer operation

Figure 8-26. Flowchart of Receive Bank Switching ID Detection Buffer Operation

01B

00B

Idle state

2-bit store & shift

1-bit store & shift

Set buffer to 00H

Bit judgment enable

Set TOSTAT

Bit judgment mask

Sync1 detection

signal = 1?

EOP received?

Store bit ?

Set DASTAT

Set HSSTAT

11B 10B

TOSTAT: Bit 0 of packet receive status register (RXSTAT)

DASTAT: Bit 1 of packet receive status register (RXSTAT)

HSSTAT: Bit 2 of packet receive status register (RXSTAT)

Main Page

Default Chapter10
- Table of Contents10
Chapter 1 General21
- Features21
- Applications21
- Ordering Information21
- Pin Configuration (Top View)22
- 0S Series Lineup23
- Block Diagram26
- Functions27
Chapter 2 Pin Functions28
- List of Pin Functions28
- Pin Functions30
- Pin I/O Circuits and Recommended Connection of Unused Pins33
  - Pin I/O Circuits34
Chapter 3 Cpu Architecture35
- Memory Space35
- Processor Registers40
- Instruction Address Addressing48
- Operand Address Addressing51
Chapter 4 Port Functions57
- Port Functions57
- Port Types57
- Functions of Ports58
- Port Configuration59
- Registers Controlling Port Function69
- Port Function Operation72
Chapter 5 Clock Generator73
- Clock Generator Functions73
- Clock Generator Configuration73
  - Block Diagram of Clock Generator73
  - Configuration of Clock Generator73
- Register Controlling Clock Generator74
  - Format of Processor Clock Control Register74
- System Clock Oscillators75
- Clock Generator Operation77
- Changing Setting of CPU Clock78
  - Time Required for Switching CPU Clock78
  - Switching CPU Clock78
    - Switching of CPU Clock78
    - Maximum Time Required for Switching CPU Clock78
Chapter 6 8-Bit Timer/Event Counters 00 and 0179
- Functions of 8-Bit Timer/Event Counters 00 and 0179
  - Interval Time of 8-Bit Timer 0079
  - Interval Time of 8-Bit Timer/Event Counter 0179
- Configuration of 8-Bit Timer/Event Counters 00 and 0180
- Registers Controlling 8-Bit Timer/Event Counters 00 and 0182
- Operation of 8-Bit Timer/Event Counters 00 and 0185
- Notes on Using 8-Bit Timer/Event Counters 00 and 0190
  - Start Timing of 8-Bit Timer Counter90
  - Timing of External Event Counter Operation90
Chapter 7 Watchdog Timer91
- Watchdog Timer Functions91
  - Inadvertent Loop Detection Time of Watchdog Timer91
  - Interval Time91
- Watchdog Timer Configuration92
  - Block Diagram of Watchdog Timer92
  - Configuration of Watchdog Timer92
- Registers Controlling Watchdog Timer93
  - Format of Timer Clock Select Register 293
  - Format of Watchdog Timer Mode Register94
- Watchdog Timer Operation95
Chapter 8 Usb Function97
- USB Overview97
  - USB Bus Topology (Desktop Type PC)97
- USB Function Features98
- USB Function Configuration98
- Registers Controlling USB Function109
- USB Function Operation122
- Interrupt Request from USB Function127
- USB Function Control130
  - Relationship between Packets and Operation Modes130
  - Interrupt Servicing Flow136
- USB Function Internal Circuit Operations140
Chapter 9 Serial Interface 10154
- Functions of Serial Interface 10154
- Configuration of Serial Interface 10155
  - Block Diagram of Serial Interface 10156
- Register Controlling Serial Interface 10157
  - Format of Serial Operation Mode Register 10157
  - Operating Mode Settings of Serial Interface 10158
- Operation of Serial Interface 10159
Chapter 10 Regulator162
- Block Diagram of Regulator and USB Driver/Receiver162
Chapter 11 Interrupt Functions163
- Interrupt Function Types163
- Interrupt Sources and Configuration163
  - Interrupt Source List164
  - Basic Configuration of Interrupt Function165
- Registers Controlling Interrupt Function166
- Interrupt Servicing Operation171
Chapter 12 Standby Function178
- Standby Function and Configuration178
- Standby Function Operation180
Chapter 13 Reset Function186
- Block Diagram of Reset Function186
- Reset Timing by RESET Input187
- Reset Timing by Overflow in Watchdog Timer187
- Reset Timing by RESET Input in STOP Mode187
- Hardware Status after Reset188
- Μ Μ Μ Μ PD78F9801190
CHAPTER 14 Μ Μ Μ Μ PD78F9801190
- Flash Memory Characteristics191
Chapter 15 Instruction Set200
- Operation200
- Operation List202
- Instructions Listed by Addressing Type207
Chapter 16 Electrical Specifications210
Chapter 17 Package Drawings219
Chapter 18 Recommended Soldering Conditions220
- Surface Mounting Type Soldering Conditions220
Appendix Adevelopment Tools221
- A-1 Development Tools222
- Software Package223
  - A.1 Software Package223
- Language Processing Software223
- Control Software224
  - A.3 Control Software224
- Flash Memory Writing Tools224
- Debugging Tools (Hardware)225
- Debugging Tools (Software)226
- Notes on Target System Design227
  - A-2 Distance between In-Circuit Emulator and Conversion Adapter227
  - A-3 Connection Condition of Target System (NP-H44GB-TQ)228
Appendix Bregister Index229
- B.1 Register Index (Alphabetic Order of Register Name)229
- B.2 Register Index (Alphabetic Order of Register Symbol)231
Appendix C Revision History233

NEC switch - Receive Bank Switching ID Detection Buffer Operation; Flowchart of Receive Bank Switching ID Detection Buffer Operation

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