Video Input
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 87
10.1.1 CSI D-PHY Design Guidelines
Table 10-6 details the signal routing requirements for CSI D-PHY interface.
Table 10-6. MIPI CSI D-PHY Interface Signal Routing Requirements
Parameter Requirement Units Notes
Max Data Rate (per data lane)
High-Speed mode
Max Frequency (for Low Power mode)
2.5
10
Gbps
MHz
Number of Loads 1 load
Max Loading (per pin)
pF
Reference plane
Breakout Region Impedance (Single Ended) 45-50 Ω ±15%
Max PCB breakout delay 48 ps
Trace Impedance Diff pair / Single Ended 90-100 / 45-50 Ω
Via proximity (Signal to reference) < 3.8 (24) mm (ps) See Note 1
Trace spacing - Microstrip / Stripline 2x / 2x dielectric
Max Insertion loss
1 Gbps
1.5 Gbps
2.5 Gbps
3.10
2.96
2.17
dB
Max trace delay / length (Stripline/Microstrip)
1 Gbps
1.5 Gbps
2.5 Gbps
3000 (435) / 2610 (435)
2242 (325) / 1953 (325)
1173 (170) / 1018 (170)
ps (mm)
Max Trace Delay Skew between DQ & CLK
1 / 1.5 / 2.5 Gbps
40/26.7/16
ps
See Note 2
Noise Coupling Avoidance
Keep critical traces away from other signal traces or unrelated power
traces/areas or power supply components
Notes:
1. Up to 4 signal vias can share a single GND return via
2. If routing to device includes a flex or 2nd PCB, the max trace and skew calculations must include all the PCBs/flex routing
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