Nvidia Jetson AGX Xavier Series User Manual

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Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 88
10.1.2 CSI C-PHY Mode Design Guidelines
Table 10-7 details the signal routing requirements for CSI C-PHY interface.
Table 10-7. MIPI CSI C-PHY Interface Signal Routing Requirements
Parameter Requirement Units Notes
Max Data Rate (per trio) 1.7 Gsps See note 1 and 2
Topology Point-Point With RX Common Mode cap to GND
Termination
Fully ODT (on-
die)
50ohms SE to common mode cap
Max Loading (per pin)
2
pF Single ended
Trace Impedance - Differential / Single Ended 90-100 / 45-50 Ω ±15%
Reference Plane
GND
Max PCB breakout Length/Delay 5 (30) mm (ps)
Via proximity (Signal via to GND return via) < 2 mm
Intra Trio Trace spacing - Microstrip / Stripline 2x / 3x dielectric Recommendation
Inter Trio Trace spacing - Microstrip / Stripline 2x / 3x dielectric
Recommend routing with loosely coupled
differential impedance.
Max Trace Length total
Direct from module conn. to device pins
1.7Gsps
1.3Gsps
One conn. between module conn. and device
1.7Gsps
1.3GSps
Two conn. between module conn. and device
1.3Gsps
180
330
100
250
150
mm
Max Intra-Trio Skew (Within Trios) 3 ps A or B pin to C pin skew.
Max Inter-Trio Skew (between Trios)
55
ps
Routing Layer Restrictions
A trio must route completely on the same layer. This means that both Trio0 and
Trio1 would need to route on the same layer due to DPHY Compatibility (e.g.
D0P/D0N must route on the same layer as CLKP/CLKN and thus so must
D1P/D1N)
Noise Coupling Avoidance
Keep critical traces away from other signal traces or unrelated power traces/areas
or power supply components
Notes:
1. Bit rate in bps is 2.286 * Gsps.
2. Maximum data rate may be limited by use case / memory bandwidth.
Table 10-8. MIPI CSI Signal Connections
Module Pin Name
Type
Termination
Description
CSI[7:0]_CLK+/–
DIFF IN
See note
CSI Differential Clocks: Connect to clock pins of camera. See the CSI
configurations tables for details
CSI[7:0]_D[1:0]+/–
DIFF IN
See note
CSI Differential Data Lanes: Connect to data pins of camera. See the
CSI configurations tables for details
Note: Depending on the mechanical design of the platform and camera modules, ESD protection may be necessary. In addition,
EMI control may be needed. Both are shown in the Camera Connection Example diagram. Any EMI/ESD solution must be
compatible with the frequency required by the design.

Nvidia Jetson AGX Xavier Series Specifications

General

GPU	512-core Volta GPU with Tensor Cores
CPU	8-core ARM v8.2 64-bit CPU, 8MB L2 + 4MB L3
Memory	32GB 256-Bit LPDDR4x | 137GB/s
Storage	32GB eMMC 5.1
DL Accelerator	2x NVDLA Engines
Vision Accelerator	7-way VLIW Vision Processor
Dimensions	105 mm x 105 mm
AI Performance	32 TOPS (INT8)
Connectivity	10/100/1000 BASE-T Ethernet
PCIe	16x PCIe Gen4
USB	USB 3.1, USB 2.0
Power	10W / 15W / 30W
Display	eDP