Nvidia Jetson AGX Xavier Series

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Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 21

Figure 5-3. Power Down Sequence Controlled Case

CARRIER_POWER_ON

VDDIN_PWR_BAD_N

SYS_VIN_HV ( VCC_SRC)

Car ri er Board P ower

(VDD_1V8, VDD_3V3)

Module P ower

SYS_RESET_N

MODULE_POWER_ON

SYS_VIN_MV

VIN_PWR_ON

Note: SYS_VIN_MV must go below 100 mV before system can be powered on again.

Figure 5-4. Power Down Sequence Uncontrolled Case

CARRIER_POWER_ON

VDDIN_PWR_BAD_N

SYS_VIN_HV ( VCC_SRC)

Carrier Board System Power

Module Power

SYS_RESET_N

SYS_VIN_MV

MODULE_POWER_ON

VIN_PWR_ON

Note: SYS_VIN_MV must go below 100 mV before system can be powered on again.

Main Page

default chapter7
- Table of Contents7
Chapter 1. Introduction16
- References16
- Abbreviations and Definitions16
- Table 1-1. Abbreviations and Definitions17
Chapter 2. Jetson AGX Xavier18
- Table 2-1. Jetson AGX Xavier Specifications18
- Figure 2-1. System Block Diagram19
- Table 2-2. Connector Pinout Matrix Part 1: Columns A-F20
- Table 2-3. Connector Pinout Matrix Part 2: Columns G-L21
Chapter 3. Main Connector Details23
- Figure 3-1. 699-Pin Connector Dimensions23
- Connector Pin Orientations24
- Figure 3-2. 699-Pin Connector Pin Orientations24
- Module to Carrier Board Spacing Details25
- Figure 3-3. 5.5 MM Height on Carrier Board - Molex Part # 203456000325
- Figure 3-4. 2.5 MM Height on Carrier Board - Molex Part # 204843000125
- Module to Carrier Board Standoff Height Recommendations26
- Table 3-1. Standoff Height Calculations for 5.5 MM Height Connector Case26
- Module Installation and Removal27
- Table 3-2. Standoff Height Calculations for 2.5 MM Height Connector Case27
- Figure 3-5. Module Removal28
Chapter 4. Reference Design Considerations29
Chapter 5. Power31
- Table 5-1. Power, System, and Thermal Pin Descriptions31
- Supply Allocation33
- Figure 5-1. Power Block Diagram33
- Table 5-2. Internal Power Subsystem Allocation33
- Power Sequencing34
- Figure 5-2. Power up Sequence - Power Button Case35
- Figure 5-3. Power down Sequence Controlled Case36
- Figure 5-4. Power down Sequence Uncontrolled Case36
- SYS_VIN_HV Input37
- Power-On37
- Power-On no MCU37
- Figure 5-5. Simplified DC Jack Power Connections37
- Auto Power-On Option no MCU38
- Figure 5-6. Simplified Button Power-On Circuitry38
- Table 5-3. Simplified Button Power Circuitry Timing38
- Power Button Supervisor MCU Power-On39
- Figure 5-7. Optional ACOK Circuitry39
- Table 5-4. Power Button Supervisor Control Signals39
- Defined Behaviors40
- Power off -> Power on (Power Button Case)40
- Figure 5-8. Power-On Button Circuit40
- Power off -> Power on (Auto-Power-On Case)41
- Figure 5-9. Power-OFF to on Sequence Power Button Case41
- Table 5-5. Power-OFF to on Timing Power Button Case41
- Power on -> Power off (Power Button Held Low > 10 Seconds)42
- Figure 5-10. Power-OFF to on Sequence Auto Power-On Case42
- Table 5-6. Power-OFF to on Timing Auto Power-On Case42
- Power Discharge43
- DV/Dt Circuit Considerations43
- Figure 5-11. Power-On to off Power Button Held Low > 10 Seconds43
- Table 5-7. Power-On to off Timing Power Button Held Low > 10 Seconds43
- Power and Voltage Monitoring45
- Power Loss Detection45
- Figure 5-12. Power Discharge45
- Power Monitor46
- Figure 5-13. VIN Loss Detection Circuit46
- Figure 5-14. Power Monitor46
- Deep Sleep or SC747
- Table 5-8. Jetson AGX Xavier Signal Wake Events47
Chapter 6. General Routing Guidelines49
- Signal Name Conventions49
- Table 6-1. Signal Type Codes49
- Routing Guideline Format50
- Signal Routing Conventions50
- Routing Guidelines50
- General PCB Routing Guidelines51
- Figure 6-1. Signal Routing Example51
Chapter 7. USB, Pcie, and UFS52
- Table 7-1. USB 2.0 Pin Descriptions52
- Table 7-2. UPHY Data Lane Pin Descriptions USB 3.1, Pcie, and UFS52
- Table 7-3. NVHS for Pcie X8 Data Lan Pin Descriptions53
- Table 7-4. Pcie Clock and Control Pin Descriptions54
- Table 7-5. UFS and Miscellaneous USB Control Pin Descriptions55
- Table 7-6. USB 3.1, Pcie and UFS Lane Mapping Configurations55
- Usb56
- Figure 7-1. Simple USB Type a Connection Example56
- Figure 7-2. Jetson AGX Xavier Carrier Board Design USB Type C Connection Example57
- Figure 7-3. USB 3.1 USB Micro AB Connection Example57
- USB 2.0 Design Guidelines58
- USB 3.1 Design Guidelines58
- Table 7-7. USB 2.0 Interface Signal Routing Requirements58
- Table 7-8. USB 3.1 Interface Signal Routing Requirements58
- Common USB Routing Guidelines61
- PCI Express62
- Table 7-9. USB 2.0 Signal Connections62
- Table 7-10. USB 3.1 Signal Connections62
- Table 7-11. Recommended USB Observation Test Points for Initial Boards62
- Figure 7-4. Pcie Root Port Connection Example63
- Figure 7-5. Pcie Endpoint Connection Example64
- Pcie Design Guidelines up to Gen365
- Table 7-12. Pcie Interface Signal Routing Requirements up to Gen365
- Figure 7-6. Insertion Loss S-Parameter Plot (SDD21)67
- Pcie Gen4 Design Guidelines68
- Table 7-13. Pcie Gen4 Interface Signal Routing Requirements68
- Table 7-14. Pcie Signal Connections Module I/Fs Configured as Root Ports69
- Table 7-15. Pcie Signal Connections Module I/F Configured as Endpoint71
- Table 7-16. Recommended Pcie Observation Test Points for Initial Boards71
- Ufs72
- UFS Design Guidelines72
- Figure 7-7. UFS Connections Example72
- Table 7-17. UFS Interface Signal Routing Requirements72
- Table 7-18. UFS Signal Connections73
Chapter 8. Gigabit Ethernet74
- Table 8-1. Jetson AGX Xavier Gigabit Ethernet Pin Descriptions74
- Figure 8-1. Ethernet Connections75
- Figure 8-2. Gigabit Ethernet Magnetics and RJ45 Connections75
- Table 8-2. RGMII Interface Signal Routing Requirements76
- Table 8-3. Ethernet MDI Interface Signal Routing Requirements76
- Table 8-4. Ethernet Signal Connections77
- Table 8-5. Recommended Gigabit Ethernet Observation Test Points for Initial Boards77
Chapter 9. Display78
- Table 9-1. Jetson AGX Xavier HDMI, Edp, and DP Pin Description78
- Table 9-2. DP and HDMI Pin Mapping79
- DP and Edp80
- Figure 9-1. DP and Edp Connection Example80
- DP and Edp Routing Guidelines81
- Figure 9-2. DP and Edp Differential Main Link Topology81
- Table 9-3. DP and Edp Main Link Signal Routing Requirements81
- Hdmi84
- Table 9-4. DP and Edp Signal Connections84
- Table 9-5. Recommended DP and Edp Observation Test Points for Initial Boards84
- Figure 9-3. HDMI Connection Example85
- Figure 9-4. HDMI CLK and Data Topology86
- Table 9-6. HDMI Interface Signal Routing Requirements86
- Table 9-7. HDMI Signal Connections91
- Table 9-8. Recommended HDMI and DP Observation Test Points for Initial Boards91
Chapter 10. Video Input92
- Mipi Csi92
- Table 10-1. Jetson AGX Xavier CSI Pin Description92
- Table 10-2. Jetson AGX Xavier Camera Miscellaneous Pin Description95
- Table 10-3. CSI Configurations D-PHY Mode95
- Table 10-4. CSI Configurations C-PHY Mode - X2 and X497
- Table 10-5. CSI Configurations C-PHY - X3 and X198
- Figure 10-1. Camera Control Connections99
- Figure 10-2. Camera CSI D-PHY Connections100
- Figure 10-3. Camera CSI C-PHY Connections101
- CSI D-PHY Design Guidelines102
- Table 10-6. MIPI CSI D-PHY Interface Signal Routing Requirements102
- CSI C-PHY Mode Design Guidelines103
- Table 10-7. MIPI CSI C-PHY Interface Signal Routing Requirements103
- Table 10-8. MIPI CSI Signal Connections103
- SLVS Camera Interface104
- Table 10-9. Miscellaneous MIPI Camera Connections104
- Table 10-10. Recommended CSI Observation Test Points for Initial Boards104
- Table 10-11. Jetson AGX Xavier SLVS EC Camera Pin Description104
- Figure 10-4. SLVS Connections106
- SLVS Design Guidelines107
- Table 10-12. SLVS Interface Signal Routing Requirements107
- Table 10-13. SLVS Camera Signal Connections108
- Table 10-14. Non-Module SLVS Reference Clock Connections108
Chapter 11. SDIO and SD Card109
- SD Card109
- Table 11-1. SDIO, SD Card, and Emmc Interface Mapping109
- Table 11-2. Jetson AGX Xavier SDMMC Pin Descriptions109
- Figure 11-1. Micro SD Card Socket Connection Example110
- Table 11-3. SDCARD Interface Signal Routing Requirements110
- Table 11-4. SD Card Loading Vs. Drive Type111
- Table 11-5. SDCARD Signal Connections112
- Table 11-6. Recommended SDCARD Observation Test Points for Initial Boards112
Chapter 12. Audio113
- Table 12-1. Jetson AGX Xavier Audio Pin Description113
- Table 12-2. I2S Interface Mapping114
- Figure 12-1. Audio Device Connections115
- I2S Design Guidelines116
- Table 12-3. I2S Interface Signal Routing Requirements116
- Table 12-4. I2S and Miscellaneous Codec Signal Connections116
- DMIC Design Guidelines117
- Table 12-5. DMIC Interface Signal Routing Requirements117
- Table 12-6. DMIC Signal Connections117
Chapter 13. Miscellaneous Interfaces118
- I2C118
- Table 13-1. Jetson AGX Xavier I2C Pin Description118
- Table 13-2. I2C Interface Mapping119
- I2C Design Guidelines120
- Figure 13-1. I2C Connections120
- Table 13-3. I2C Interface Signal Routing Requirements121
- Table 13-4. I2C Signal Connections121
- Bounce122
- Spi122
- Table 13-5. De-Bounce Settings - Fast Mode Plus, Fast Mode, and Standard Mode122
- Table 13-6. Jetson AGX Xavier SPI Pin Description122
- SPI Design Guidelines123
- Figure 13-2. SPI Connections123
- Figure 13-3. Basic SPI Master and Slave Connections123
- Figure 13-4. SPI Point-Point Topology123
- Figure 13-5. SPI Star Topologies123
- Figure 13-6. SPI Daisy Topologies124
- Table 13-7. SPI Interface Signal Routing Requirements124
- Table 13-8. SPI Signal Connections124
- Table 13-9. Recommended SPI Observation Test Points for Initial Boards124
- Uart125
- Table 13-10. Jetson AGX Xavier UART Pin Description125
- Figure 13-7. Jetson AGX Xavier UART Connections126
- Table 13-11. UART Signal Connections126
- Can127
- Figure 13-8. Jetson AGX Xavier CAN Connections127
- Table 13-12. Reserved UART4_RX Routing Requirements127
- Table 13-13. Jetson AGX Xavier CAN Pin Description127
- Table 13-14. CAN Interface Signal Routing Requirements128
- Table 13-15. CAN Signal Connections128
Chapter 14. Fan129
- Table 14-1. Jetson AGX Xavier Fan Pin Description129
- Figure 14-1. Jetson AGX Xavier Fan Connection Example130
- Table 14-2. Fan Signal Connections130
Chapter 15. Debug and Strapping131
- USB Recovery Mode131
- JTAG and Debug UART132
- Figure 15-1. JTAG and UART Debug Connections132
- Figure 15-2. Simple Debug UART Header Connections132
- Jtag133
- Table 15-1. Jetson AGX Xavier JTAG Pin Description133
- Table 15-2. JTAG Signal Connections133
- Debug UART134
- Strapping Pins134
- Table 15-3. Debug UART Connections134
- Table 15-4. Strapping Pins134
- Boundary Scan Test Mode135
- Figure 15-3. Example Buffer between Pin Associated with Soc Strap and Connected Device135
- Figure 15-4. Boundary Scan Connections135
- Safety MCU Jaxi Only136
- Table 15-5. Safety MCU Related Partial Pin Descriptions136
- Figure 15-5. Safety MCU Connections137
Chapter 16. Pads138
- MPIO Pad Behavior When Associated Power Rail Is Enabled138
- Schmitt Trigger Usage138
- Pins Pulled and Driven During Power-On138
- Pad Drive Strength139
- Table 16-1. MPIO Maximum Output Drive Current139
Chapter 17. Unused Interface Terminations140
- Unused MPIO Interfaces140
- Unused SFIO Interface Pins140
- Table 17-1. Unused MPIO Pins and Pin Groups140
Chapter 18. Design and Bring-Up Checklists141
Chapter 19. General Layout Guidelines142
- Via Guidelines142
- Via Count and Trace Width142
- Via Placement142
- Via Placement and Power and Ground Corridors142
- Figure 19-1. Via Placement for Good Power Distribution143
- Figure 19-2. Good Current Flow Resulting from Correct Via Placement143
- Figure 19-3. Poor Current Flow Resulting from Incorrect Via Placement143
- Connecting Vias144
- Trace Guidelines144
- Layer Stack-Up144
- Trace Length144
Chapter 20. Stack-Ups145
- Reference Design Stack-Ups145
- Importance of Stack-Up Definition145
- Impact of Stack-Up Definition on Design145
Chapter 21. Transmission Line Primer146
- Basic Board Level Transmission Line Theory146
- Characteristics146
- Figure 21-1. Typical Transmission Lin Circuit146
- Physical Transmission Line Types147
- Microstrip Transmission Line147
- Stripline Transmission Line147
- Figure 21-2. Microstrip Transmission Line147
- Figure 21-3. Stripline Transmission Line147
- Drive Characteristics148
- Receiver Characteristics148
- Transmission Lines and Reference Planes149
- Figure 21-4. Transmission Line Height149
- Figure 21-5. Crosstalk on Reference Plane150
- Figure 21-6. Power Plane Cuts Example150
- Figure 21-7. Power Plane Cuts Example When Decouple Capacitors Are Abundant150
- Figure 21-8. Switching Reference Planes151
- Figure 21-9. Reference Plane Switch Using Via151
Chapter 22. Design Guideline Glossary152

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