Power
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 19
Power Rails Usage (V) Power Supply Source
VDDIO_AO_3V3 SoC VDDIO_AUDIO_HV and VDDIO_AO_HV rails 3.3 PMIC LDO2 SYS_VIN_MV
VDD_EMMC_3V3 eMMC device 3.3V rail 3.3 PMIC LDO3 SYS_VIN_MV
VDD_USB_3V3 SoC AVDD_USB rail 3.3 PMIC LDO5 SYS_VIN_MV
VDD_SDIO_3V3
SoC VDDIO_SDMMC1_HV and
VDDIO_SDMMC3_HV rails
3.3 PMIC LDO6 SYS_VIN_MV
DDR_VDD2_1.1V SoC VDDIO_VDD2_DDRx and DRAM VDD2 rails. 1.1 LTC3636 SYS_VIN_HV
VDD_DDRQ VDDIO_DDRxLV and LPDDR4x VDDQ rails 0.6 LPDDR4x
LTC3636 SYS_VIN_HV
Notes:
1. SoC AVDD_PLL_NVHS_EUTMIP, VDD_HDMI_DP_PLL_0_1/1_3, PEX_HVDD, NVHS0_HVDD and NVHS0_PLL0_HVDD rails
2. SoC VDDIO_UART/AUDIO/SDMMC4/DMMC3_HV_VCLAMP/ VDDIO_SDMMC1_HV_VCLAMP/CONN/EQOS/QSPI/,
AVDD_PLL_AA1_CV_ADC/DD2D3D4DPHBCS/CC2C3PADC_BPMP/C4_REFE, eMMC device VCCQ and QSPI device VDD rails.
3. These rails are sourced from the PMIC Switcher SD2 used for VDDIO_SYS_1V8LS which is sourced from SYS_VIN_MV.
4. SoC VDDIO_EDP/PEX_CTL/DEBUG/CAM/AO/VREFR0/ SYS, VPP_FUSE, AVDD_PLL_AON/MSC/GADC_M/MSD/XADC_MSB,
VCLAMP_USB, AVDD_OSC, LPDDR4x device VDD1, Temp Sensor VDD
5. Enable (RUN2 pin) for VDD_DDRQ supply and Enable for discharge of DDR_VDD2_1.1V,
VDDIO_SYS_1V8HS/SYS_1V8LS/AO_1V8 rails.
5.2 Power Sequencing
The following list describes the basic power on sequencing requirements.
ï‚„ The main power source for the system is applied. The
SYS_VIN_HV and SYS_VIN_MV are
derived from this power source. Optionally, these supplies can be gated and only enabled
to the module when a signal (such as
VIN_PWR_ON) is enabled. This can help avoid damage
if the module is inserted when main power is on.
ï‚„
VDDIN_PWR_BAD_N should stay active (low) until both SYS_VIN_HV/MV are valid (and not
gated).
ï‚„
MODULE_POWER_ON can be set active (high) once VDDIN_PWR_BAD_N is inactive (high).
ï‚„ As the module powers on, one of the last supplies is the 3.3V supply always-on supply.
CARRIER_POWER_ON is pulled up to the powergood pin of the 3.3V supply. Once this signal is
active (high), the carrier board supplies associated with the module (1.8V, 3.3V) can power
on.
ï‚„
SYS_RESET_N is driven by the PMIC on the module during power-on. It does not need to be
controlled by the carrier board. If the carrier board supplies required for powering on
require additional time, the
PERIPHERAL_RESET_N signal can be held low. This will keep the
SoC and other boot devices in reset.
To Next Page
Loading...
Need help?
General
