Nvidia Jetson AGX Xavier Series - Page 13

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xiii
List of Tables
Table 1-1. Abbreviations and Definitions ................................................................................ 2
Table 2-1. Jetson AGX Xavier Specifications .......................................................................... 3
Table 2-2. Connector Pinout Matrix Part 1: Columns A-F..................................................... 5
Table 2-3. Connector Pinout Matrix Part 2: Columns G-L .................................................... 6
Table 3-1. Standoff Height Calculations for 5.5 mm Height Connector Case .................... 11
Table 3-2. Standoff Height Calculations for 2.5 mm Height Connector Case .................... 12
Table 5-1. Power, System, and Thermal Pin Descriptions .................................................. 16
Table 5-2. Internal Power Subsystem Allocation ................................................................. 18
Table 5-3. Simplified Button Power Circuitry Timing .......................................................... 23
Table 5-4. Power Button Supervisor Control Signals .......................................................... 24
Table 5-5. Power-OFF to On Timing Power Button Case .................................................... 26
Table 5-6. Power-OFF to On Timing Auto Power-On Case ................................................. 27
Table 5-7. Power-On to OFF Timing Power Button Held Low > 10 Seconds ...................... 28
Table 5-8. Jetson AGX Xavier Signal Wake Events ............................................................... 32
Table 6-1. Signal Type Codes ................................................................................................ 34
Table 7-1. USB 2.0 Pin Descriptions ..................................................................................... 37
Table 7-2. UPHY Data Lane Pin Descriptions USB 3.1, PCIe, and UFS .............................. 37
Table 7-3. NVHS for PCIe x8 Data Lan Pin Descriptions ..................................................... 38
Table 7-4. PCIe Clock and Control Pin Descriptions ........................................................... 39
Table 7-5. UFS and Miscellaneous USB Control Pin Descriptions ..................................... 40
Table 7-6. USB 3.1, PCIe and UFS Lane Mapping Configurations ...................................... 40
Table 7-7. USB 2.0 Interface Signal Routing Requirements ............................................... 43
Table 7-8. USB 3.1 Interface Signal Routing Requirements ............................................... 43
Table 7-9. USB 2.0 Signal Connections ................................................................................ 47
Table 7-10. USB 3.1 Signal Connections ................................................................................ 47
Table 7-11. Recommended USB Observation Test Points for Initial Boards ....................... 47
Table 7-12. PCIe Interface Signal Routing Requirements up to Gen3 .................................. 50
Table 7-13. PCIe Gen4 Interface Signal Routing Requirements ........................................... 53
Table 7-14. PCIe Signal Connections Module I/Fs Configured as Root Ports ...................... 54
Table 7-15. PCIe Signal Connections Module I/F Configured as Endpoint .......................... 56
Table 7-16. Recommended PCIe Observation Test Points for Initial Boards ....................... 56
Table 7-17. UFS Interface Signal Routing Requirements ..................................................... 57
Table 7-18. UFS Signal Connections ...................................................................................... 58
Table 8-1. Jetson AGX Xavier Gigabit Ethernet Pin Descriptions ........................................ 59
Table 8-2. RGMII Interface Signal Routing Requirements .................................................. 61
Table 8-3. Ethernet MDI Interface Signal Routing Requirements ...................................... 61
Table 8-4. Ethernet Signal Connections ............................................................................... 62