USB, PCIe, and UFS
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 51
GEN1/GEN2: Min/Max
GEN3: Min/Max
0.075 / 0.265
0.176 / 0.265
0.1uF or 0.22uF recommended for
GEN1 or GEN2. 0.22uF recommended
for GEN3. Only required for TX pair
Location (max length to adjacent discontinuity)
Discontinuity such as edge finger,
component pad
Voiding the plane directly under the
pad 3-4 mils larger than the pad
size is recommended.
Serpentine (See USB 3.1 Guidelines)
Voiding the plane directly under
the pad 5.7 mils larger than the
pad size is recommended.
Keep critical PCIe traces such as PEX_TX/RX, TERMP etc. away from other signal traces or unrelated power traces/areas or
power supply components
Notes:
1. The PCIe spec. has 40-60Ω absolute min/max trace impedance, which can be used instead of the 50Ω, ± 15%.
2. If routing in the same layer is necessary, route group TX and RX separately without mixing RX/TX routes and keep distance
between nearest TX/RX trace and RX to other signals 3x RX-RX separation.
3. For trace loss >= 0.7dB/in @ 2.5GHz, the max trace length should be 7 inches. To reduce trace loss, ensure the loss tangent
of the dielectric material and roughness of the metal are tightly controlled.
4. The average of the differential signals is used for length matching.
5. Do length matching before Via transitions to different layers or any discontinuity to minimize common mode conversion.
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