USB, PCIe, and UFS
Jetson AGX Xavier Series Product DG-09840-001_v2.5 | 55
• Use zig-zag route
instead of straight to
minimize skew, this is
a mandatory for PCIe
gen4 design
Trace Spacing (Stripline)
Pair – Pair
To plane and capacitor pad
To unrelated high-speed signals
4x
4x
4x
Dielectric
TX and RX should not be routed on the
same layer. If this is required in a design,
they should not be interleaved, and the
spacing between the closest RX and TX
lanes must be 9x Dielectric spacing.
Breakout region (Max Length)
Minimum width and spacing. 4x or wider
dielectric height spacing is preferred
Trace loss budget (for carrier board routing)
Routing direct to device
Routing to PCIe/M.2 connector
-19
-13.5
dB/in
@ 4GHz (See TBD),
Loss: GEN4 budget – module – end device
(-28dB + 5dB + 4dB)
Loss: GEN3 budget – module – end device
(-28dB + 5dB + 9.5dB)
Max trace length (delay)
Direct to device on carrier board
Stripline
Microstrip
Routed to PCIe or M.2 connector
Stripline
Microstrip
357 (2463)
328 (1939)
254 (1750)
233 (1378)
in (ps)
Mid-loss PCB of 1.47dB/in (Microstrip) or
1.35dB/in (Stripline) is used. Also,
6.9ps/mm for Stripline routing and
5.9ps/mm for Microstrip.
Max PCB via distance from the
Device/Connector
Max distance from Device ball or Connector
pin to first PCB via.
PCB within pair (intra-pair) skew
Do trace length matching before hitting
discontinuities.
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled length
Place GND vias as symmetrically as possible to data pair vias. GND via distance should
be placed less than 1x the diff pair via pitch
Use micro via or back drilled via - no via stub
allowed.
20%, 0402 X5R or better. Only required
for TX pair when routed to connector.
Place close to TX side.
Voiding the plane directly under
the pad 3-4 mils larger than the
pad size is required.
Serpentine (See USB 3.1 Guidelines)
Remove unwanted GND fill that is either floating or act like antenna
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